427 Ips Jobs - Page 17

We are seeking a skilled and proactive Cyber Security Engineer to protect our organizations systems, networks, and data from cyber threats. The ideal candidate will be responsible for developing security measures, responding to incidents, and ensuring compliance with industry regulations. You have: Bachelor s degree in cyber security, Computer Science, Information Technology, or related field. 1-2 years of experience with security tools (SIEM, IDS/IPS, EDR, firewalls). Knowledge of network security, encryption, authentication, and cloud security. Understanding of ethical hacking, penetration testing, and forensic analysis. It would be nice if you also had: Experience with cloud security (AWS, Azure, Google Cloud). Knowledge of secure coding practices and DevSecOps. Familiarity with security frameworks and regulatory requirements. Industry certifications preferred (CISSP, CISM, CEH, CompTIA Security etc.). Monitor, detect, and respond to cyber threats, vulnerabilities, and attacks. Implement security measures such as firewalls, encryption, and endpoint protection. Conduct security assessments, penetration testing, and risk analysis. Develop and enforce security policies, procedures, and best practices. Ensure compliance with industry standards (ISO 27001, NIST, GDPR, HIPAA, etc.). Investigate security incidents and provide incident response and forensic analysis. Collaborate with IT and other departments to strengthen cybersecurity posture. Provide cybersecurity awareness training to employees. Stay up to date with the latest security threats, trends, and technologies.

2-3 years of experience in IT security monitoring, detecting, and escalating security incidents, and Patch management. Familiarity with one of the SIEM platforms (Fortinet, LogRhythm, Azure Sentinel, CrowdStrike) Basic knowledge of endpoint protection tools like CrowdStrike, Symantec, Defender for Endpoint. Exposure to firewalls, IDS/IPS, and DLP solutions, Understanding of TCP/IP, DNS, DHCP, NAT, and VPN. Familiar with the OSI model, port numbers, common protocols, and basic Log Analysis, Threat Intelligence. Awareness of Common attack types: phishing, malware, brute-force, DoS, MITRE ATT& Teamwork: Ability to coordinate with L2/L3 teams or network/security admins. Assist in basic forensic data collection if needed.

At Pitney Bowes, we do the right thing, the right way. As a member of our team, you can too. We have amazing people who are the driving force, the inspiration and foundation of our company. Our thriving culture can be broken down into four components: Client. Team. Win. Innovate. We actively look for prospects who: Are passionate about client success. Enjoy collaborating with others. Strive to exceed expectations. Move boldly in the quest for superior and best in market solutions. Job Description: Join Pitney Bowes as a Senior Software Engineer (SOC Analyst) Years of experience: 2 - 5 years Job Location - Pune You are: A Decisive Contributor who can support and enrich an enterprise-wide incident identification and resolution program. You are a Determined individual who thrive on investigations, and you deliver with precision. You see opportunities where others see challenges. You will: Actively drive IT Security response engagements to completion Ability to support and validate security requirements of IT solutions Participate in and support a team of 9+ SOC analysts and subject matter experts Actively participate in development of cyber security offerings Consult on operational practices to protect information Participate in proactive threat hunting to detect incidents Guide and mentor fellow analysts with investigation and mitigation of security threats and incidents. Monitor security consoles and ticket queues for events, and drive to resolution Learn, support and enrich new security platforms in an enterprise environment Work in a 24x7, fast paced environment with best-in-industry IT Security incidents and technologies Your background: As a SOC Analyst, you have: 3 - 6 years of experience in security incident response and technical forensics investigation 2 - 5 years of experience in IT Network or Cyber Operations Incident handling and forensics skills including knowledge of common probing and attack methods, network/service discovery, system assessment, viruses and other forms of malware. Ability to monitor and analyze SIEM, endpoint, network (Firewall,IPS), and application logs Extensive documentation skills with Excel, PowerPoint and ticketing systems Ability to prepare reports of analysis and results to provide briefings to management Skills in performing and optimizing operational processes Technical expertise in supporting modern and cutting-edge security technologies Preferred Bachelor s degree in information security, Computer Science or equivalent Information Security Certifications such as CISSP, CRISC, and/or CISM Experience interfacing with other internal or external organizations regarding failure and incident response situations Knowledgeable and experienced in: SIEM (Exabeam) or other UEBA platform IDS/IPS (Cisco/Sourcefire/Palo) EDR (CrowdStrike) Email Security (Proofpoint) IRT Coordination SOC/MSS Daily Threat Dashboard Reporting MITRE Framework implementation and auditing Scripting and automation About Pitney Bowes Pitney Bowes (NYSE:PBI) is a global technology company providing commerce solutions that power billions of transactions. Clients around the world, including 90 percent of the Fortune 500, rely on the accuracy and precision delivered by Pitney Bowes solutions, analytics, and APIs in the areas of ecommerce fulfillment, shipping and returns; cross-border ecommerce; office mailing and shipping; presort services; and financing. For 100 years Pitney Bowes has been innovating and delivering technologies that remove the complexity of getting commerce transactions precisely right. For additional information visit Pitney Bowes at https://www.pitneybowes.com/in . Only Talent Matters at Pitney Bowes Pitney Bowes is an equal opportunity workplace. To remove unconscious biases from our hiring process, we encourage Blind Applications from candidates applying for jobs at Pitney Bowes. This means that details such as gender, caste, religion, nationality, and age are omitted from applications. And candidates can choose to reveal only their first or last name on the application. Watch the video here: https: / / www.youtube.com / watchv=dNB-K5KFU78 Watch the videos below for more information about Life at Pitney Bowes: Who we are Pitney Bowes All Stars Pitney Bowes named a Great Place to Work Pitney Bowes Gratitude Video Pitney Bowes COVID Care Pitney Bowes was the recipient of several coveted Awards: We will: Provide the will: opportunity to grow and develop your career Offer an inclusive environment that encourages diverse perspectives and ideas Deliver challenging and unique opportunities to contribute to the success of a transforming organization Offer comprehensive benefits globally ( P B Live Well ) Pitney Bowes is an equal opportunity employer that values diversity and inclusiveness in the workplace. All interested individuals must apply online.

At Pitney Bowes, we do the right thing, the right way. As a member of our team, you can too. We have amazing people who are the driving force, the inspiration and foundation of our company. Our thriving culture can be broken down into four components: Client. Team. Win. Innovate. We actively look for prospects who: Are passionate about client success. Enjoy collaborating with others. Strive to exceed expectations. Move boldly in the quest for superior and best in market solutions. Job Description: Join Pitney Bowes as a Security Operations Lead Years of experience: 10+ years Job Location - Pune Impact A Proactive Leader who can Develop and manage an enterprise-wide incident identification and resolution program . You are a l oyal individual who thrive s on investigation, and deliver s with precision. You see opportunities where others see challenges. The Job Actively lead multiple engagements simultaneously and seamlessly Ability to identify, provide and validate security requirements of IT solutions Lead a team of 9+ SOC analysts and subject matter experts Actively participate in development of cyber security offerings Be the Trusted Advisor on best practices to protect information Provide proactive threat hunting to detect incidents Guide and mentor L1 and L2 analysts with investigation and mitigation of security threats and incidents. Perform information security best practice audits on platforms and processes Deploy and operationalize new security platforms in an enterprise environment Qualifications & Skills required 5 years of experience leading teams utilizing a Security Incident Event Management Solution 10 years of experience in security incident response and technical forensics investigation Incident handling and forensics skills including knowledge of common probing and attack methods, network/service discovery, system assessment, viruses and other forms of malware. Ability to monitor and analyze SIEM, endpoint, network (Firewall,IPS), and application logs Extensive documentation skills with Excel, PowerPoint and ticketing systems Ability to prepare reports of analysis and results to provide briefings to management Ability to perform MITRE ATT&CK Mapping Skills in building, managing and auditing operational processes Technical expertise in supporting modern and cutting-edge security technologies Knowledgeable and experienced in: SIEM (Exabeam) IDS/IPS (Cisco/Sourcefire/Palo) EDR (CrowdStrike/Defender) IRT Coordination SOC/MSS The MITRE ATT&CK framework Daily Threat Dashboard Reporting FluentBit implementation or comparable JIRA Service Desk Confluence Preferred Skills Bachelor s degree in information security , Computer Science or equivalent Information Security Certifications such as CISSP, CRISC, and/or CISM Experience interfacing with other internal or external organizations regarding failure and incident response situations About Pitney Bowes Pitney Bowes (NYSE:PBI) is a global technology company providing commerce solutions that power billions of transactions. Clients around the world, including 90 percent of the Fortune 500, rely on the accuracy and precision delivered by Pitney Bowes solutions, analytics, and APIs in the areas of ecommerce fulfillment, shipping and returns; cross-border ecommerce; office mailing and shipping; presort services; and financing. For 100 years Pitney Bowes has been innovating and delivering technologies that remove the complexity of getting commerce transactions precisely right. For additional information visit Pitney Bowes at https://www.pitneybowes.com/in . Only Talent Matters at Pitney Bowes Pitney Bowes is an equal opportunity workplace. To remove unconscious biases from our hiring process, we encourage Blind Applications from candidates applying for jobs at Pitney Bowes. This means that details such as gender, caste, religion, nationality, and age are omitted from applications. And candidates can choose to reveal only their first or last name on the application. Watch the video here: https: / / www.youtube.com / watchv=dNB-K5KFU78 Watch the videos below for more information about Life at Pitney Bowes: Who we are Pitney Bowes All Stars Pitney Bowes named a Great Place to Work Pitney Bowes Gratitude Video Pitney Bowes COVID Care We will: Provide the will: opportunity to grow and develop your career Offer an inclusive environment that encourages diverse perspectives and ideas Deliver challenging and unique opportunities to contribute to the success of a transforming organization Offer comprehensive benefits globally ( P B Live Well ) Pitney Bowes is an equal opportunity employer that values diversity and inclusiveness in the workplace. All interested individuals must apply online.

Job Profile -Expert level technical support for network security product. -Handling customer technical escalations. -Troubleshooting, diagnosing and resolving technical customer issues. -Recreating, tracking, and verifying software defects in the field or under lab conditions reported by customers. -Authoring technical knowledge base articles for use by other technical support personnel and/or customers and partners. Skill sets desired Advanced Networking Skills - Detailed understanding of the protocols surrounding IP service provider networks. Strong network security skills required. Networking skills should include: a. TCP/IP fundamentals b. IP subnetting and supernetting and hierarchical routing principles c. Routing protocol operation (BGP) d. Routing policies at BGP peering points e. VPNs and the associated tunneling technologies (GRE/IP. L2TP, MPLS, etc.) f. Hands-on configuration and operational knowledge of Cisco and Juniper routers g. Hands-on Understanding and knowledge of Netflow, SNMP Security skills DDOS, IPS, IDS, Threat detection and mitigation Operating systems - Basic to Intermediate knowledge of Linux Database: Basic to Intermediate knowledge of database - postgres, sqlite Good to have: Scripting - shell and/or high level languages (Python, Perl, Php) Other: Customer focused candidate, strong attention to detail, ability to establish and maintain strong working relationships with key internal and customer personnel to work effectively. Outstanding customer service and advanced written and verbal communications skills.

Job Description: Consultant_SuccessFactors Architect: Responsibilities: Ability to design, create and manage SuccessFactors Report stories Working knowledge of IAS and IPS configuration. Experience working as part of project team and Production support team. Strong working knowledge of SuccessFactors reporting tools. Ability to troubleshoot and update existing SuccessFactors Dashboards Ability to drive requirements, configuration, testing and production deployment with business and IT stakeholders Ability to support Release feature meetings for SuccessFactors Reporting tools Ability to drive Employee central Solution Design and Configuration of MDF objects, Workflows and Business rules. SuccessFactors certification(s) preferred Experience with other SuccessFactors module such as LMS is a plus. Strong verbal and Written Communication skills. Additional Sills:

As part of the Enterprise Security team, the Security Technology Operations (STO) Manager will help secure Arm s digital infrastructure. This includes managing and optimizing security technologies, implementing Zero Trust and network segmentation, and enhancing threat detection and response. The role requires strong cloud and network security knowledge, hands-on experience with security tools, and the ability to lead strategic initiatives while coordinating with partners, vendors, and internal teams. Responsibilities Implement network segmentation and Zero Trust to reduce attack surfaces, enforce least-privilege access, and isolate systems across enterprise and cloud environments. Lead the deployment, optimization, and upkeep of tools like EDR, AV, DLP, VPN, and firewalls to improve Arm s security posture. Promote Zero Trust principles identity-based access control, continuous verification, micro-segmentation, and clear trust boundaries to limit lateral movement and protect key assets. Collaborate with architects and infrastructure teams to define segmentation policies that align with Arm s threat model. Drive enhancements to security technologies, ensuring compliance with standards like NIST, CIS, and ISO 27001. Partner with IT and security teams to roll out new technologies and extend Zero Trust and segmentation across environments. Mentor analysts and engineers, promoting a culture of proactive defense and secure-by-design practices. Required Skills and Experience Demonstrated ability in security operations, infrastructure security, or network security roles. Strong expertise in network security technologies, including VPN, firewalls, IDS/IPS, Zero Trust Network Access (ZTNA) , and segmentation strategy and implementation . Technical proficiency in security solutions, including EDR, DLP, AV, email security, and cloud-native security controls. Experience implementing Zero Trust frameworks and network segmentation architectures in hybrid or multi-cloud environments. Understanding of Identity and Access Management (IAM) systems, including least-privilege access models, directory services, and policy-based access control. Familiarity with ITIL processes, security governance, and risk management, with experience tracking SLAs and compliance objectives. Nice to Have Skills & Certifications Security certifications such as CISSP, CISM, CCSP, AWS Certified Security, or Cisco Certified CyberOps Professional. Experience with scripting and automation for operational efficiency (e.g., Python, PowerShell, Terraform), as well as modern Infrastructure-as-Code and Policy-as-Code frameworks. Familiarity with Zero Trust security models, segmentation technologies (e.g., SDN, NGFWs, NAC) , and continuous risk assessment techniques.

Configuration, fault, performance, availability, backup, and capacity management of all SOC Security devices. Configure, deploy, and maintain NGFW solutions to protect network infrastructure. Develop, implement, and manage security policies, rules, and access controls. Firewall rule additions to be performed daily following SAR process. Design and implement segmentation strategies using VLANs, zones, and security policies. Co-ordination with internal teams such as NOC for firewall rule base management and troubleshooting. Analyze firewall performance, troubleshoot issues, and optimize configurations. Participate in security architecture planning and integration of new devices in DC and DR. Policy/Rule Management and configuration optimization of security devices such as Firewalls etc. Periodic review the backup configuration and business continuity procedures to be followed in the event of Device failure. Maintain IP addressing schemes, routing information, routing tables, for the Device operations Service uptime assurance of all security devices. Open a case with device supplier in the event of hardware component or system failure or bugs. Work with SIEM, IDS/IPS, VPNs, and other security solutions for comprehensive protection. Technical Expertise: Strong experience with NGFW like Fortinet & Check Point. Proficiency in firewall rule configuration, VPNs, NAT, threat prevention, upgradation and URL filtering etc. Understanding of networking protocols (TCP/IP, DNS, BGP, OSPF, etc.).

Roles & Responsibilities: Triage alerts and analyze security events/logs for threats such as computer viruses, exploits, and malicious attacks. Use critical thinking to bring together information from multiple sources to determine if a threat is present. Conduct security incident response and investigation. Conduct comprehensive security assessments and risk analysis on existing systems and applications. Analyze web traffic for suspicious patterns and potential security breaches. Perform vulnerability assessments and penetration testing. Prepare and provide security documentation and evidence for internal and external audits, ensuring compliance with regulatory requirements and security standards. Stay abreast of the latest cybersecurity trends, threats, and technologies to proactively address emerging risks. Bachelor s degree in computer science, Information Technology, cybersecurity, or a related field. 3+ years of relevant experience. Proficiency in conducting risk assessments, vulnerability assessments, and penetration testing.

Job Title Security Operations Analyst Location Bangalore, Karnataka, India What you will do As a Security Operations Analyst, you will play a critical role in monitoring and responding to security incidents, identifying vulnerabilities, and ensuring compliance with security policies. You will collaborate with various stakeholders to enhance the security posture of our organization and support incident response activities. How you will do it Monitor security alerts and events from various security tools and platforms. Investigate security incidents, perform root cause analysis, and document findings. Assist in the management of security incidents, including containment, eradication, and recovery efforts. Conduct regular security assessments and vulnerability scans to identify potential risks. Collaborate with IT and other departments to remediate vulnerabilities and implement security best practices. Support incident response activities and maintain incident response documentation. Participate in security awareness training and educate staff on security policies and procedures. Stay updated with the latest security trends, threats, and technologies. What we look for Bachelors degree in computer science, Information Technology, Cybersecurity, or a related field. 4-6 years of experience in security operations, incident response, or a related field. Strong understanding of security frameworks and best practices (e. g. NIST, ISO 27001). Experience with security tools such as SIEM, IDS/IPS, and vulnerability management solutions. Knowledge of networking protocols and systems security concepts. Excellent analytical and problem-solving skills. Strong communication skills and the ability to work collaboratively in a team environment. Relevant cybersecurity certifications (e. g. CompTIA Security+, CEH, CISSP) are a plus. What we offer Competitive salary and performance-based bonuses. Comprehensive benefits package including health, dental, and retirement plans. Opportunities for professional development and continuous learning. Collaborative and inclusive work environment.

Job Description: Consultant SuccessFactors Architect Responsibilities: Ability to design, create and manage SuccessFactors Report stories Working knowledge of IAS and IPS configuration. Experience working as part of project team and Production support team. Strong working knowledge of SuccessFactors reporting tools. Ability to troubleshoot and update existing SuccessFactors Dashboards Ability to drive requirements, configuration, testing and production deployment with business and IT stakeholders Ability to support Release feature meetings for SuccessFactors Reporting tools Ability to drive Employee central Solution Design and Configuration of MDF objects, Workflows and Business rules. SuccessFactors certification(s) preferred Experience with other SuccessFactors module such as LMS is a plus. Strong verbal and Written Communication skills

GRC Lead will manage and strengthen our Governance, Risk, and Compliance (GRC) initiatives for Managed Security Services (MSS) within the Telecom sector. The GRC Lead will be responsible for ensuring that the services we provide to our telecom clients adhere to industry standards, regulatory requirements, and robust risk management practices. This individual will play a key role in aligning our security services with client business objectives, improving our security posture, and ensuring compliance with telecom-specific regulations and frameworks. You have: 7+ years of experience in Governance, Risk, and Compliance (GRC), with at least 3 years in telecom or Managed Security Services (MSS) with a degree in Telecommunication Engineering, Computer Science, Information Security, or a related field (B.E/B.Tech/M.E/M.Tech/MCA). Expertise in telecom-specific security technologies: Firewalls, IDS/IPS, SIEM, encryption, access management, and incident response platforms. Experience working with security and compliance frameworks: ISO 27001, NIST CSF, PCI-DSS, GDPR, NIST SP 800-53, ETSI EN 303 645, also telecom infrastructure, including MPLS, 5G, IoT, and SDN/NFV. Familiarity with GRC tools such as RSA Archer, ServiceNow GRC, or MetricStream. Experience in telecom risk management processes, regulatory assessments, and vendor risk governance. It would be nice if you also had: Industry certifications such as CISM, CISA, CISSP, CRISC, ISO 27001 Lead Auditor/Implementer, TOGAF, or ITIL. Experience in stakeholder management, including executive communication, regulatory liaison, and conflict resolution with auditors or vendors. Strong analytical, negotiation, and project management skills in a cross-functional, multicultural telecom environment. Provide security governance leadership tailored to telecom networks, including mobile, 5G, SDN/NFV, and MPLS environments. Lead risk assessment, threat modeling, and management activities for telecom networks and emerging technologies like IoT and cloud. Ensure compliance with global and local telecom regulatory requirements (e.g., TRAI, DoT, GDPR, FCC, ETSI) through audits, reviews, and reporting. Manage and maintain telecom-specific security policies, technical and administrative controls, and compliance frameworks (ISO 27001, NIST, PCI-DSS). Act as the prime security and compliance interface towards customers, internal teams, auditors, subcontractors, and third-party suppliers. Develop and maintain a risk register, tracking treatment plans and mitigation strategies across client environments. Provide proactive consultation and guidance to customers regarding security best practices and compliance requirements. Oversee incident and crisis response activities to minimize business impact and regulatory exposure, ensuring adherence to notification guidelines. Ensure vendor security due diligence, contract compliance, and ongoing third-party risk monitoring within the telecom supply chain.

"> Search Jobs Find Jobs For Where Search Jobs SOC Engineering, Staff Engineer Noida, Uttar Pradesh, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 8601 Remote Eligible No Date Posted 22/04/2025 Alternate Job Titles: Staff SOC Engineer Senior SOC Design Engineer Lead SOC Engineer We Are: You Are: You are an experienced and motivated SOC Engineer with a passion for cutting-edge technology and innovation. With a strong background in system-on-chip (SOC) design and verification, you bring a wealth of knowledge and a keen eye for detail. You thrive in a collaborative environment, working seamlessly with cross-functional teams to deliver high-quality solutions. Your problem-solving skills are exceptional, and you have a proven track record of successfully managing complex projects. You are proactive, adaptable, and always eager to learn and grow in a dynamic and fast-paced setting. What You ll Be Doing: Designing and implementing SOC solutions for various applications, ensuring high performance and reliability. Collaborating with cross-functional teams to define and develop SOC architecture and specifications. Conducting verification and validation of SOC designs to ensure compliance with industry standards and customer requirements. Optimizing SOC designs for power, performance, and area (PPA) to meet project objectives. Debugging and resolving issues in SOC designs, utilizing advanced tools and methodologies. Providing technical guidance and mentorship to junior engineers, fostering a culture of continuous improvement and innovation. Job Description and Requirements The role is for RTL Design and Signoff of IP/Subsystem/SoC Design in the System Solutions Group (SSG). At SSG, we are a team of experts in various Synopsys technologies to deliver architecture, design, verification, implementation, tools, methodology to enable our customers complete their most challenging SoC Design projects. Our work spans from sub-blocks to full turnkey end-to-end SoCs. Our customers range from start-ups to industry leaders, commercial companies, and government agencies. As part of this role, you can expect to develop and deliver your expertise in RTL Signoff and RTL Design Techniques while working on activities such as Lint/CDC/RDC Checks, Timing Constraints Development, Preliminary Synthesis, Formality and RTL Design. The role will expose you to various innovative technologies deployed for RTL Quality Signoff for Semiconductors. Responsibilities Perform RTL Quality Signoff Checks such as LINT, CDC, RDC. Understand the design/architecture and develop timing constraints for synthesis and timing. Run preliminary synthesis to ensure that the design can be synthesized as intended. Run formality to ensure equivalence of RTL and gates. Integrate IPs in SoCs/Subsystems and create RTL design as per need of the customer. Required B.E/B. Tech/M.E/M. Tech in electronics with 4-9 years experience in RTL Design and Verification. Hands-on experience on static verification tools such as Spyglass performing LINT, CDC, RDC. Good conceptual understanding of design/architecture pitfalls across clock/reset domain crossing. Good conceptual understanding of RTL rule checks. Hands-on experience on synthesis and timing constraints development. Candidates with experience on ARM based technologies (Coresight Debug, Processor architecture, etc.) will be preferred. The Team You ll Be A Part Of: You will join a highly skilled and motivated team dedicated to developing advanced SOC solutions. Our team focuses on innovation, collaboration, and excellence, working together to deliver high-quality designs that drive technological advancements. We value diversity and inclusion, fostering a supportive and dynamic environment where every team member can thrive and contribute to our success. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. *Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Noida View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

We are seeking innovative and out-of-the-box thinking Design For Test (DFT) Engineers to be a part of the Fast Solution Team under the Test Group at Synopsys. You are someone who thrives in a project-oriented environment, delivering comprehensive DFT solutions ranging from integration to silicon bring-up for customers designing digital ICs of varying complexity. You excel in assessing customer methodologies and flows, gathering requirements, and proposing solutions. You are adept at providing technical support to ensure customer success and satisfaction, winning new customers through product demonstrations, evaluations, and competitive benchmarking. You are skilled in resolving technical problems, training, and account management, and you can interact effectively with end-users at customer sites and with first-level managers. You are also responsible for working with Solution Architects to develop and productize the next-gen test technologies. Your role involves prototyping new methodologies, analyzing gathered data, identifying the viability of technology, and presenting the findings under the guidance of a Solution Architect. What You ll Be Doing: Providing expertise for test solutions during design planning, budgeting, and implementation. MBIST implementation and validation, including BIST architecture planning, memory grouping, pattern generation, validation, silicon bring-up, diagnostics analysis, and debug. Participating in customer s design and flow reviews. Driving, prototyping, and developing new Design for Test methodologies. Multitasking across various issues and priorities to help customers exploit new technologies. Collaborating with Solution Architects to develop and productize next-gen test technologies. The Impact You Will Have: Enhancing Synopsys ability to deliver cutting-edge test solutions that meet customer needs. Contributing to the successful integration and silicon bring-up of complex digital ICs. Ensuring high customer satisfaction through effective technical support and problem resolution. Driving innovation in test methodologies and technologies. Supporting the development of next-gen test technologies that push the boundaries of whats possible. Playing a key role in winning new customers and expanding Synopsys market presence. What You ll Need: Minimum BS+10 years of relevant experience/MS+8 years of relevant experience in Electrical Engineering, Computer Engineering, or other relevant fields of study. Experience with RTL coding, DFT insertion, ATPG, MBIST architecture planning, insertion, validation, pattern generation, and silicon bring-up. Excellent knowledge of memory BIST flows, memory fault models, MBIST algorithms, hard/soft repair, and eFuse repair flow. Experience in handling memory BIST for large, complex SoCs with various IPs. Exposure to MBIST of automotive designs is a plus. Good understanding of protocols like 1149.1, 1500, 1687.

Working on producing highly optimized hardware IP for the ARC family of configurable processors. Collaborating with an international multi-disciplinary team on the qualification, benchmarking, and test chip implementation of new microprocessor IPs. Participating in in-house test chip designs and development platforms to learn about potential applications of our microprocessor IPs. Assisting in customer sales and design-ins of our IP, providing technical support and expertise. Implementing a comprehensive implementation flow that is configurable and supported by Synopsys memory compilers and standard cell libraries. Ensuring the highest standards of quality in physical verification and IR processes. The Impact You Will Have: Contributing to the development of cutting-edge microprocessor IPs that set industry standards. Enhancing the capabilities of our customers by enabling them to develop highly sophisticated embedded designs. Driving the success of our products through your expertise in physical verification and IR. Supporting our sales team by providing technical insights and facilitating design-ins. Improving the efficiency and configurability of our implementation flows. Helping to position Synopsys as a leader in the semiconductor industry through continuous innovation. What You ll Need: Bachelor s degree in electronics engineering or computer science; Master s degree is a plus. Minimum of 5 years of related experience in physical verification and IR. Proficiency in Verilog/VHDL. Expertise in Unix, Perl, and TCL scripting. Understanding of microprocessor design is highly desirable. Who You Are: A detail-oriented professional with strong analytical skills. An excellent communicator with the ability to convey complex technical concepts effectively. A team player who thrives in a collaborative, international environment. A proactive learner who stays updated with the latest industry trends and technologies. A problem solver who enjoys tackling challenging technical issues

The candidate would be part of the VIP group responsible for development of Verification IPs. Core responsibilities would include Designing and developing the VIP/Test-bench, Creating Verification plans, Coding sequences/Test-scenarios, Coverage driven verification. The responsibility would also include enhancement of the existing Verification IP products and interface with customers during VIP deployment. This is an opportunity to work with best-in-class verification, debug tools, Design IP & close collaboration with best protocol experts in the industry. You will work with highly professional and motivated colleagues who value and support your contribution. Requirements: Bachelors/masters with good academic record. 7+ years experience in developing HVL based verification environments, preferably using System Verilog. Exposure to coverage driven verification. Experience in verification methodologies like UVM/OVM. Exposure to complex SV test benches involving multiple protocols and VIPs. Experience in VIP development is highly desirable. Should have a strong work exposure on any of the industry standard protocols like PCIe, USB, Ethernet, MIPI etc.. Demonstrates good analysis and problem-solving skills. Have a strong passion for work and driving things to closure.

Implementing and power signoff of world-class DDRs at cutting-edge technology nodes. Achieving timing closure above ~2GHz and integrating mixed signal macro IPs. Building efficient clock trees with very tight skew balancing. Providing regular updates to your manager on project status. Guiding junior peers with aspects of their job and contributing to their development. Representing the organization on business unit and/or company-wide projects. The Impact You Will Have: Driving the implementation of cutting-edge DDR technology, contributing to the advancement of high-performance computing. Ensuring the power efficiency and performance of our silicon chips, crucial for our competitive edge. Enhancing the reliability and integration of mixed signal macro IPs. Contributing to the overall success and innovation of Synopsys IP solutions. Mentoring junior engineers, fostering a culture of continuous learning and improvement. Representing Synopsys in key projects, influencing the direction and success of our initiatives. What You ll Need: Minimum of 5+ years of related experience in ASIC Physical Design. Proficiency in tools like DC, ICC2, StarRC, and PT-SI. Strong understanding of timing closure, power signoff, and mixed signal macro IP integration. Experience with DDR power signoff and clock tree building. Excellent problem-solving and analytical skills. Who You Are: A strong team player with excellent communication skills. Independent and collaborative, capable of working with minimal supervision. Creative and innovative, able to develop unique solutions to complex problems. Detail-oriented and organized, ensuring high-quality project outcomes. Passionate about continuous learning and professional growth.

We are looking for a highly motivated individual, with expertise in IC design and physical implementation for a group with growth opportunities. Responsibilities include complete digital implementation from RTL to GDS including Synthesis, Floor-Planning, Power Planning and Analysis, CTS, Placement and Routing, STA, Formal Verification, EMIR Signoff and physical verification. The individual will contribute both on the implementation side as well as flow development for a variety of advanced high performance interface IPs, Test chips & Subsystems at latest techno nodes. The successful candidate: - has solid engineering understanding of the underlying concepts of IC design, implementation flows and sign-off methodologies for deep submicron design. - has intimate knowledge of the full design cycle from RTL to GDSII, including development of timing constraints - has good scripting & programming skills (Perl, Tcl, Python etc); knowledge of CAD automation methods. - Can interface with the larger product team to understand design constraints, deliverable formats, customer requirements - Independent, timely decision maker and able to cope with interrupts - Knowledge of IP Subsystem implementation & FE flows are added advantages 8+ years of hands-on experience in ASIC physical implementation and EDA tools with recent contribution to project tape-outs. Must demonstrate knowledge of the Synopsys tools, flows and methodologies including Design Compiler, IC Compiler/2, Fusion Compiler, Primetime, Formality, Star-RCXT, Hercules/ICV and other industry tools.

Driving the physical implementation of high-speed interface IPs and test-chips from RTL to GDS. Managing timing and physical sign-off to ensure successful project tape-outs. Collaborating with multiple functional groups, including front-end, analog, and CAD teams. Focusing on advanced SerDes developments, including the latest 56/112G PAM4 standards. Leading the physical design team to ensure on-time delivery of projects. Utilizing your software and scripting skills to enhance CAD automation methods. The Impact You Will Have: Contributing to the successful delivery of high-performance silicon IPs that power the Era of Smart Everything. Ensuring the integration of more capabilities into SoCs, meeting unique performance, power, and size requirements. Reducing the risk and time-to-market for differentiated products. Driving technological innovation through advanced SerDes development. Enhancing Synopsys reputation as a leader in chip design and verification. Supporting the companys mission to power the world s most advanced technologies for chip design and software security. What You ll Need: 8+ years of physical design experience with recent contributions to project tape-outs. Intimate understanding of the full design cycle from RTL to GDSII, including chip level. Experience with advanced FinFET nodes, TSMC 16 nanometer or below. Solid understanding of IC design, implementation flows, and methodologies for deep submicron design. Proven track record for technical steering of physical design teams for on-time delivery. Who You Are: Excellent communicator with the ability to engage with peer groups and customers. Autonomous and capable of making timely judgments. Proficient in software and scripting skills (Perl, Tcl, Python). Knowledgeable in CAD automation methods and industry standards in deep sub-micron designs. Able to travel internationally as required.

Designing and verifying complex Analog Mixed-Signal layouts, ensuring high-quality and reliable IPs. Collaborating with cross-functional teams to optimize layout designs for performance and manufacturability. Utilizing advanced tools and methodologies to mitigate deep submicron effects. Conducting floor-planning, routing, and top-level verification. Ensuring compliance with DRC, LVS, LPE standards and addressing ESD and latch-up considerations. Optimizing power routes and addressing EM and IR considerations for robust designs. The Impact You Will Have: Enhancing the performance and reliability of our high-speed SerDes IPs and other critical components. Driving innovation in Analog Mixed-Signal layout design, contributing to cutting-edge technology developments. Ensuring seamless integration and functionality of our IPs in diverse applications. Improving design efficiency and manufacturability through advanced layout techniques. Contributing to the success of our product development lifecycle by delivering high-quality designs. Supporting our mission to lead in chip design and IP integration, shaping the future of technology. What You ll Need: 6+ years of experience in Analog Mixed-Signal layout and verification. Advanced understanding of deep submicron effects and mitigation techniques. Proficiency in using advanced layout design tools and methodologies. Solid understanding of CMOS and FinFET layouts and process technology in 28nm and below. Familiarity with layout design flow, including top-level verification flow, DRC/LVS, LPE.

Developing next-generation high-speed memory interface PHY IPs (DDR/HBM/UCIe) Executing projects in advanced technologies with a focus on analytical and problem-solving skills Designing high-speed IOs for memory interface PHY IP in CMOS/FinFET/GAA Collaborating with cross-functional teams globally to achieve project goals Ensuring product quality and efficiency in all design tasks Staying updated with the latest industry standards and technological advancements The Impact You Will Have: Driving the development of innovative high-speed memory interface PHY IPs Contributing to the integration of advanced capabilities in SoCs Enhancing the performance, power efficiency, and size optimization of target applications Reducing risk and accelerating time-to-market for differentiated products Collaborating with global teams to deliver high-quality products Setting industry benchmarks for advanced analog design technologies What You ll Need: BTech/MTech degree in a relevant field 3+ years of experience in analog design fundamentals and device physics Proficiency in high-speed IO designs in advanced technologies Experience with ESD and reliability concepts Knowledge of JEDEC requirements for memory interfaces and standards Familiarity with signal integrity and/or power integrity is a plus Who You Are: An analytical thinker with strong problem-solving skills A collaborative team player with excellent communication and interpersonal skills Detail-oriented and capable of executing tasks with high precision and efficiency Adaptable and eager to learn new technologies and industry standards Passionate about innovation and technological advancement

We are seeking an experienced analog design manager to lead our high-performance SERDES IP design team. This senior role will oversee all aspects of analog IP development and execution for cutting-edge SerDes architectures targeting advanced process nodes. Responsibilities: - Manage and mentor a team of 8-10 senior analog designers focused on high-speed SerDes IP development across multiple projects - Define architecture specifications and circuit implementation requirements for next-generation SerDes PHY IPs - Ensure adherence to project schedules, quality metrics, power/area targets through effective team oversight - Collaborate with cross-functional teams (digital design, physical design, CAD) to integrate analog IP components - Partner with process engineering teams to enable robust analog IP across advanced FinFET nodes - Continuously drive design methodology improvements and adoption of latest EDA tools/flows - Develop and manage operational plan, including staffing, budgets and resource allocation - Hire, develop and retain top analog engineering talent through active mentorship Requirements: - Bachelors degree in electrical engineering; advanced degree preferred -8+ years of experience in analog/mixed-signal IC design with a strong background in SerDes architectures - 2+ years of people management experience leading high-performance analog design teams - Proven expertise in high-speed I/O design, architectures, circuits, and layout implementation - Extensive knowledge of CDR, DFE, CTLE, EQ, decision feedback equalizer design techniques - Hands-on experience with analog/mixed-signal design flows, tools (Cadence, Synopsys), modeling - Understanding of FinFET transistor characteristics and design challenges at advanced nodes - Strong project management skills with the ability to manage multiple priorities - Excellent communication and people leadership abilities to motivate cross-functional teams

Leading the development of next-generation high-speed memory interface IPs (DDR/HBM/UCIe). Driving projects in new technologies with a focus on analytical and problem-solving skills. Acting as a technical mentor to ensure schedules and product quality are met. Developing and maintaining project schedules, working in cross-functional settings. Demonstrating proficiency in design concepts and methodologies. Taking on people management responsibilities, guiding and developing your team. The Impact You Will Have: Contributing to the development of cutting-edge memory interface PHY IPs that drive technological advancements. Ensuring high-quality product development through effective leadership and technical expertise. Mentoring and guiding your team to achieve their full potential and meet project goals. Collaborating with cross-functional teams to drive innovation and efficiency. Maintaining Synopsys leadership position in the semiconductor industry by delivering top-notch IPs. Shaping the future of technology through continuous innovation and excellence. What You ll Need: Bachelor s or Master s degree in Electrical Engineering or related field. 10+ years of experience in analog/mixed signal design. Knowledge of deep submicron process technologies - CMOS/FinFET/GAA. In-depth understanding of JEDEC requirements for memory interfaces and standards. Familiarity with ESD concepts and signal integrity/power integrity is a plus. Proven ability to lead projects and deliver high-quality products efficiently. Excellent written and verbal communication skills. Who You Are: A visionary leader with a passion for analog design and innovation. Analytical and detail-oriented with strong problem-solving skills. An effective communicator and mentor, capable of guiding and developing your team. Proactive and adaptable, able to thrive in cross-functional settings. Committed to delivering high-quality products and driving technological advancements.

Leading the development of next-generation DDR/HBM/UCIe IPs. Advising team members to meet schedules and resolve problems effectively. Taking on project leadership roles and contributing to complex project aspects. Developing and maintaining project schedules, ensuring timely delivery. Collaborating in cross-functional settings to drive project success. Demonstrating proficiency in design and verification processes. The Impact You Will Have: Driving innovation in next-generation DDR/HBM/UCIe IP development. Enhancing the performance and capabilities of our Silicon IP portfolio. Ensuring high-quality and efficient project execution. Mentoring and guiding team members to achieve their full potential. Contributing to the rapid integration of advanced technologies into SoCs. Helping Synopsys maintain its leadership in the semiconductor industry. What You ll Need: Bachelor s or Master s degree in Electrical Engineering or a related field. 8+ years of experience in CMOS circuit design and layout methodology. In-depth understanding of analog/mixed-signal circuitry and ESD concepts. Familiarity with analog mixed-signal simulation strategies. Knowledge of JEDEC standards for DDR interfaces and ASIC design flow. Who You Are: Visionary leader with strong problem-solving skills. Excellent communicator with the ability to lead and mentor teams. Detail-oriented and proficient in project management. Adaptable and able to thrive in cross-functional settings. Committed to achieving high standards of product quality and efficiency

* Responsible for functional verification involving coherent and non-coherent IP designs. * Collaborating with market leaders in High Performance Computing, Data Centre, Mobile/Client, Automotive, and IoT segments to define and develop products that meet complex verification requirements. * Architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. * Developing verification plans and driving functional coverage-driven verification closure of real designs. * Debugging and resolving issues in verification environments to ensure robust and reliable verification processes. The Impact You Will Have: * Enhancing the reliability and performance of high-performance computing and data center systems through rigorous verification processes. * Contributing to the advancement of mobile and client devices by ensuring the integrity and functionality of their verification protocols. * Driving innovation in the automotive sector by developing robust verification solutions for automotive systems. * Supporting the growth of IoT applications by providing reliable and efficient verification for IoT devices. * Collaborating with industry leaders to shape the future of system verification and contribute to technological advancements. * Ensuring the successful implementation and integration of verification IPs, thereby enhancing the overall quality of our products. What You ll Need: * B.E/B.Tech in Electrical Engineering/Electronics & Communications Engineering with 5-8 years of relevant experience, OR M.E/M.Tech in VLSI Design/Microelectronics with 4-8 years of relevant experience. * Hands-on experience in architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs. * You will be involved in creating System verification solutions for Arm AMBA5 protocols such as CHI, AXI5/ACE5 for on-chip, chi-to-chip, die-to-die, coherent and non-coherent design topologies. * You will be responsible for functional verification involving coherent and non-coherent IP designs. * Proficiency in writing scripts using Perl, Python, and Shell scripting. Who You Are: * Excellent problem-solving, debugging, and analytical skills. * Strong programming skills and familiarity with object-oriented programming concepts. * Creative and innovative mindset. * Excellent verbal and written communication skills. * A collaborative team player with a passion for functional verification.