219 Ip Verification Jobs - Page 6

Must Have: SV/UVM, Test Bench Development , Any Protocols Must be able to own and drive the verification of a block / subsystem or a SOC. Must have extensive experience in verification Share resume to mansoor@hisoltech.com

Job Overview We are seeking an experienced and highly skilled Senior SOC Design Verification Engineer with a minimum of 5 years of hands-on experience in SOC Design Verification. As a key member of our team, you will play a pivotal role in ensuring the robustness and correctness of our cutting-edge System on Chip designs. Job Description Lead and manage SOC Design Verification efforts for complex projects, ensuring the successful execution of verification plans. Develop and implement comprehensive verification strategies, test plans, and test benches for high-speed SOCs, including low-speed peripherals like I2C/I3C, SPI, UART, GPIO, QSPI, and high-speed protocols like PCIe, Ethernet, CXL, MI...

Role & responsibilities Strong verification expertise using Verilog and SystemVerilog, with solid understanding of UVM methodology and hands-on experience writing test-benches. Proficient in debugging testcases and verifying processor-based subsystems. Knowledge of AMBA protocols (AXI, AHB, APB) is a plus. Exposure to Arm-based SoCs and strong grasp of digital design fundamentals. Experience with scripting in Perl, TCL, Make, and Shell.

We are looking for a seasoned Senior Design Verification Engineer with 8+ years of experience in verifying complex digital IPs and SoCs. The ideal candidate will have strong expertise in developing UVM-based verification environments and driving functional coverage closure. Key Responsibilities: Develop and maintain constrained-random and directed testbenches using System Verilog/UVM Define verification plans and test strategies based on specifications Write test cases, checkers, and functional coverage models Perform RTL simulations, debug failures, and ensure coverage closure Collaborate with RTL, DV, and firmware teams across verification lifecycle Support gate-level simulation, regressio...

We are hiring 8+ years of hands-on DV experience in System Verilog/UVM.

SENIOR VERIFICATION ENGINEER- SV UVM SmartSoC is looking for smart and enterprisingDesign Verification engineers to come to join us and get an opportunity to do some cutting-edge work and also work in a great environment where work is Always Fun and Exciting. SmartSoCs is currently working on multiple in-house turnkey projects and client site projects and many of our projects involve complete verification from spec to closure including building complete DV environments in SV-UVM. Job Responsibilities- Build SV, SV UVM, OVM based environments. Work with many different networking and other protocols Desired Skills and Experience- 3 to 10 years of experience in IP verification Good experience i...

VERIFICATION LEAD – IP VERIFICATION SmartSoC is looking for a smart and enterprising leader with expert knowledge in IP Verification to come and technically lead a Team. We are looking for someone who is very strong technically and very good at multi-tasking as your role will involve leading 7 to 8 projects at one time. You will be responsible for leading and managing a team, client communication, and project execution. This role will include- Lead an internal IP Verification team, executing projects for an offshore client Be responsible for Test Planning, Environment Architecture and Project Management of Multiple Projects Guide team members in verifying IP’s and delivering zero bug IP’s Ma...

Design Verification Engineer (5-7 years experience) Company: HCL Tech Job Summary: We are looking for a talented and motivated Design Verification Engineer to join our team and play a key role in ensuring the functionality and quality of our next-generation integrated circuits (ICs). This position offers the opportunity to work on challenging projects while utilizing your expertise in verification methodologies and tools. Responsibilities: Develop and implement comprehensive verification plans using industry-standard methodologies (e.g., UVM) Design and write robust verification environments (testbenches) to achieve high code coverage Utilize simulation tools (e.g., ModelSim, Cadence Incisiv...

We are hiring PCIe engineers: -In-depth knowledge and experience with PCIe protocols upto Gen5 -Good experience of system Verilog -handson experience of working on UVM -Good to have scripting language Perl/Shell/python

Hiring Design Verification Engineers for Bangalore location. Exp: 5+ Years Company: Eximietas Design Job Area: Engineering Group, Engineering Group > Hardware Engineering. Eximietas: Eximietas Design is a leading technology consulting and solutions development firm specializing in the VLSI, Cloud Computing, Cyber Security, and AI/ML domains. Our success is anchored in the unparalleled expertise of our engineering leadership team, whose collective experience spans renowned tech giants like Google, Cisco, Microsoft, Oracle, Uber, Broadcom, and Sun. With a commitment to innovation and excellence, we deliver cutting edge solutions that empower businesses to thrive in the ever-evolving digital la...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Looking for candidates between 3 to 13 years of experience. Worked on coverage driven module verification. Strong in System Verilog, UVM Sound experience in testbench (stimulus, agent, monitor, checker) development. Failure debugging with Verdi & log file. Worked in the verification having c based reference model inside the testbench Experience with assertion development. Familiar with the EDA tools IUS, VCS, Verdi etc. Exposure in scripting(perl, Python). Good team player. Need to interact with the designers and other verification engineers proactively. Prior experience with video pipeline is added advant...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: QCT's Bangalore Wireless R&D (WRD) HW team in Bangalore is looking for experienced Wireless HW design verification engineers to work on Qualcomms best in class chipsets for mobile phones, wearables and IOT . Candidate will be working with ASIC designs on the latest technology nodes. This role will require the candidate to understand and work on all aspects of VLSI Verification cycle like Testbench architecture, Verification Planning, Testbench and Test development, Verification closure with best-in-class methodologies. In this role of WRD Verification Engineer, you will be verifying Wifi and/or Modem from ...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Our team here works on the Verification of advanced IP's, HW Accelerators and Subsystem for AI/ML/DL Applications Being part of this team will give you exposure to the design and verification of latest Qualcomm AI/ML/DL IP's/Core Being a part of the DV Team, you will work on Functional , Formal Power aware and Gate level simulation Get to work on the latest and cutting-edge tech nodes Required to work on IP verification and own various DV tasks from Test plan creation, coverage model development, test case writing and coverage closure. Should be proficient in System-Verilog and scripting language like Shel...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Our team here works on the Verification of advanced IP's, HW Accelerators and Subsystem for AI/ML/DL Applications Being part of this team will give you exposure to the design and verification of latest Qualcomm AI/ML/DL IP's/Core Being a part of the DV Team, you will work on Functional , Formal Power aware and Gate level simulation Get to work on the latest and cutting-edge tech nodes Required to work on IP verification and own various DV tasks from Test plan creation, coverage model development, test case writing and coverage closure. Should be proficient in System-Verilog and scripting language like Shel...

Role Overview As a Lead Design Verification Engineer , you will own verification strategy and execution for high-complexity IP and SoC designs. You will be responsible for planning, leading teams, defining testbench architecture, and ensuring coverage-driven closure. Key Responsibilities Define and drive the verification plan based on design specifications and functional requirements. Architect and develop reusable UVM/SystemVerilog-based testbenches. Own IP/SoC-level functional verification from test planning to coverage closure. Work closely with RTL, DFT, and firmware teams for seamless integration and debug. Guide and mentor junior engineers; conduct reviews and knowledge sessions. Contr...

Job Description: We are looking for experienced DV Lead Engineers with a strong background in SystemVerilog, UVM, and protocol-based SoC/IP verification . The ideal candidate will have excellent debugging and leadership skills, with hands-on experience in building testbenches and leading verification teams. Key Responsibilities: Build comprehensive test plans , test cases , and functional coverage from specification documents Architect and develop UVM-based testbenches and verification environments Work with high-speed protocols such as AXI, AHB, APB, PCIe Hands-on debugging and simulation using Synopsys and Cadence tools Mentor junior team members, collaborate cross-functionally, and lead p...

Lead the verification planning and execution for complex SoC designs. Define and implement testbenches using SystemVerilog/UVM methodologies. Work closely with architecture, design, and firmware teams to understand the design and develop test strategies. Drive block-level and full-chip verification , including IP integration . Perform coverage analysis , debug , and triage failures . Develop and maintain automation scripts to improve verification workflows. Mentor and guide junior verification engineers and drive best practices across the team. Ensure delivery on schedule with high quality and coverage metrics.

Key Responsibilities: Hands-on microarchitecture and RTL development for IP blocks Develop microarchitecture based on design specifications, including HW-SW interface definition IP-level verification and debugging for video and audio subsystems Work on MIPI CSI and DSI protocols understanding at protocol and implementation level Collaborate with design, verification, and software teams to ensure high-quality deliverables Drive or contribute to test plan creation, environment development, and coverage closure

Design Verification Engineer (5-7 years experience) Company: HCL Tech Job Summary: We are looking for a talented and motivated Design Verification Engineer to join our team and play a key role in ensuring the functionality and quality of our next-generation integrated circuits (ICs). This position offers the opportunity to work on challenging projects while utilizing your expertise in verification methodologies and tools. Responsibilities: Develop and implement comprehensive verification plans using industry-standard methodologies (e.g., UVM) Design and write robust verification environments (testbenches) to achieve high code coverage Utilize simulation tools (e.g., ModelSim, Cadence Incisiv...

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: IP Sub system Verification Location: Bangalore Work Type: Onsite Job Type: Full time Job Description: Need verification engineers with solid verification experience(5+ year) at IP subsystem level. Good experience in SV/UVM based testbench creation, test case writing, checkers, monitors, debugs, coverage analysis. IP level verification experience preferred in high speed IOs like DDR/USB/PCIE etc. General expertise in infrastructure, tools like Perl, Python etc. Senior leads should have experience in doing hands-on as well as leadership responsibilities. Expected time...

Increasing digitalization and flexibility of production processes presents outstanding potential. In Digital Industries, we enable our customers to unlock their full potential and drive digital transformation with a unique portfolio of automation and digitalization technologies. From hardware to software to services, we’ve got quite a lot to offer. How about you We blur the boundaries between industry domains by integrating the virtual and physical, hardware and software, design and manufacturing worlds. With the rapid pace of innovation, digitalization is no longer tomorrow’s idea. We take what the future promises tomorrow and make it real for our customers today. Join us - where your caree...

Job description Design Verification Engineer (4 to 15 Years) SoC/IP Verification Company: ACL Digital (Wafer space Semiconductor) Location [Bangalore/Pune] Experience: 4 to 15 Years Openings: 4 Positions Preferred - Immediate to 45 Days (Notice Period) ACL Digital is hiring experienced Design Verification Engineers to work on leading-edge processor-based SoCs and IPs. Strong understanding of design verification methodologies (UVM, SV, etc.) Experience with industry-standard protocols (AXI, DDR, PCIe, etc.) Familiarity with ASIC and SoC design flows. Proficiency in scripting languages (Python, Perl) Experience with simulation tools and debuggers. Strong problem-solving and analytical skills C...

Job Description Job Summary: We are looking for a highly experienced and motivated Senior Design Verification Engineer with a deep understanding of the PCIe protocol and hands-on experience in SystemVerilog and UVM. The ideal candidate will lead verification activities for complex PCIe subsystems or SoCs, and contribute to building scalable, reusable verification infrastructure. Key Responsibilities: Develop UVM-based verification environments for PCIe IPs or SoCs . Define and execute comprehensive verification plans for PCIe Gen3/Gen4/Gen5/Gen6 features. Drive testbench development, stimulus generation, scoreboarding, and coverage closure. Validate protocol compliance including LTSSM, TLP/D...

As a Formal Verification Engineer at AMD, you will play a crucial role in the Advance Formal Verification team, dedicated to providing formal functional and security verification for a variety of IPs. Your expertise in IP verification, formal verification methodologies, and high-speed IO bus protocols will be instrumental in ensuring the highest level of design quality through cutting-edge formal verification technologies. Your responsibilities will include collaborating with architects and designers to understand design intents, creating and executing formal verification plans, writing and debugging properties for design verification, optimizing runtime using formal techniques, and reportin...

Dear Candidate, We are hiring for Top MNC!! Location: Pune Work Mode: Hybrid-General Shift Contract: 1 Year Required Skills As a member of the Design Verification [Pre-Silicon DV] Team for NXP WCS/SCE BU. You will be responsible for verification of various IPs and/or SoC. Candidate must be self-motivated and capable of working independently or as part of a team. You will implement simulation testbenches, low power simulation setup, assembly/C language diagnostics, assertion checkers or coverage monitors to meet target verification goals. You will also assist with developing test-plans, debugging failures and analyzing coverage information. Must have excellent knowledge of computer architectu...