183 Ip Verification Jobs - Page 2

Job Specs : - Expertise in Digital Verification - Expertise in Functional Verification - Expertise in SOC / IP Verification - Expertise in working on system Verilog assertions & test benches - Expertise in working on OVM / UVM / VMM based verification flow - Expertise in working on ARM processor - Expertise in working on AMBA bus protocols (AXI, AHB, APB) - Expertise in CXL or PCIe Protocol Verification - Expertise in simulation tools (VCS, ModelSim, Questa) - Expertise in driving Verification Strategy, writing Test Plan, developing Test Bench, Test cases. - Expertise in analysing Code Coverage, Functional Coverage and Assertions. - Expertise in verification of complex SoCs. - Expertise in T...

Job Specs : - Expertise in Digital Verification - Expertise in Functional Verification - Expertise in SOC / IP Verification - Expertise in working on system Verilog assertions & test benches - Expertise in working on OVM / UVM / VMM based verification flow - Expertise in working on ARM processor - Expertise in working on AMBA bus protocols (AXI, AHB, APB) - Expertise in CXL or PCIe Protocol Verification - Expertise in simulation tools (VCS, ModelSim, Questa) - Expertise in driving Verification Strategy, writing Test Plan, developing Test Bench, Test cases. - Expertise in analysing Code Coverage, Functional Coverage and Assertions. - Expertise in verification of complex SoCs. - Expertise in T...

Key Responsibilities Lead and execute IP and SoC-level verification using UVM/SystemVerilog methodologies Develop scalable testbenches and environments aligned with project verification goals Define and drive coverage-driven and assertion-based verification strategies Debug complex simulation failures at the testbench and RTL level Integrate verification IPs and ensure protocol compliance for interfaces like DDR5, HBM3, PCIe Gen6, CXL 3.0 Collaborate with architecture, design, firmware/software, and system validation teams Drive early software validation with virtual prototypes and emulation platforms Work on power-aware and DFT verification flows where applicable

Roles and Responsibilities Design verification using UVM, OVM, PCIe, Ethernet, Amba, USB protocols. Develop testbenches for IP verification and SOC verification. Collaborate with cross-functional teams to identify requirements and develop solutions. Conduct functional verification of designs using System Verilog and Verilog HDL. Participate in code reviews to ensure high-quality deliverables.

Expertise in Digital Verification Expertise in MAC Protocol: USB, WiFi , Bluetooth Expertise in SOC / IP Verification Expertise in working on system Verilog assertions & test benches Expertise in working on OVM / UVM / VMM based verification flow Good knowledge in gate-level simulation, and Scripting languages like Python, TCL Must be a resident of India, preferably in Bangalore or Pune

Title: Sr. Design Verification Engineer / Lead Verification Engineer Location: Offshore onsite (Pune, Ahmedabad) Duration: Full-Time MIO: Skype + F2F Looking an experienced Design Verification Engineer to join our growing team. Health insurance Annual bonus Provident fund

Job Description In this role, you will be part of the ASIC verification team responsible for functional verification of ASIC IPs. ASIC verification methodology employs state of the art techniques and tools, including coverage-driven constrained random verification and formal verification. Object-oriented architectures and frameworks are a fundamental part of how we design and implement our verification environments. Expertise and Aptitude towards verifying functions such as image processing, video compression, and computer vision. As a verification engineer, you will also have the opportunity to learn about the algorithms behind the hardware. Key Responsibilities - Responsible for functional...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Looking for candidates between 3 to 13 years of experience. Worked on coverage driven module verification. Strong in System Verilog, UVM Sound experience in testbench (stimulus, agent, monitor, checker) development. Failure debugging with Verdi & log file. Worked in the verification having c based reference model inside the testbench Experience with assertion development. Familiar with the EDA tools IUS, VCS, Verdi etc. Exposure in scripting(perl, Python). Good team player. Need to interact with the designers and other verification engineers proactively. Prior experience with video pipeline is added advant...

Role : Design Verification Work Location : Preferred Pune WFO, If candidate is found to be excellent Noida or Bangalore Remote options are open Years of Experience : 4+ Years Education Qualification : MS (or higher) in EE/EC/ECC Engineering Skills Must have excellent knowledge of computer architecture and design verification fundamentals. Must have experience with Verilog and popular EDA simulation, System Verilog assertions and testbench methodologies. Experience in developing complex test bench in System Verilog using OVM/ UVM methodology. Hands-on experience in AMBA protocol, PCIe MAC/ USB /MAC/ Bluetooth MAC/ Wifi 802.11 MAC layer protocol. Experience in Low Power Simulation/UPF setup, d...

About the Role: We are seeking an experienced Design Verification Engineer with 5 to 10 years of hands-on experience in verifying complex digital designs, particularly in IP cores, SoCs, and PCIe protocols. The ideal candidate will have deep expertise in developing and executing verification plans, writing testbenches, and automating verification environments to ensure high-quality silicon delivery. Key Responsibilities: Develop and implement comprehensive verification plans and strategies for IP, SoC, and PCIe blocks. Create and maintain advanced verification environments using SystemVerilog, UVM (Universal Verification Methodology), and other relevant methodologies. Write and debug directe...

Demonstrate a solid understanding of the CPU/CPU Based SoC Verification. Must have good understanding of one or more of the following domains ARM v8/v9, RISC-V, x86 Architecture Memory Architecture(DRAM, Cache, MMU), GIC, SoC Debug Architecture Cache Coherent Architectures PCIe OSCI Layer and its functionality PCIe Phy , Bring up and trainin SoC DV, BUS Interconnects Understand architecture and micro-architecture specifications. Work closely with Architects and Logic Designers. Develop Unit Level and/or Subsystem Level Test plans, Coverage Plans and checker Plans needed to target zero defect post-silicon quality. Develop scalable Test benches in System Verilog and UVM. Develop Tests, Functio...

What you will do Work under broad guidance and create verification plan based on the IP design specification Build Standalone IP test bench using System Verilog Develop test cases, coverage model and assertions needed to ensure functional correctness of the Design Under Test (i.e., IP/SOC) Use the IP/SOC RTL in system Verilog based logic verification environment & complete the functional verification Generate functional and code coverage metrics, collaborate with IP developers on the correctness & completeness of IP functionality. Deliver the functional test vectors needed to be used for post-silicon validation. Be the single point contact for the concerned IP Verification and enable the Tap...

Demonstrate a solid understanding of the CPU/CPU Based SoC Verification. Must have good understanding of one or more of the following domains ARM v8/v9, RISC-V, x86 Architecture Memory Architecture(DRAM, Cache, MMU), GIC, SoC Debug Architecture Cache Coherent Architectures PCIe OSCI Layer and its functionality PCIe Phy , Bring up and trainin SoC DV, BUS Interconnects Understand architecture and micro-architecture specifications. Work closely with Architects and Logic Designers. Develop Unit Level and/or Subsystem Level Test plans, Coverage Plans and checker Plans needed to target zero defect post-silicon quality. Develop scalable Test benches in System Verilog and UVM. Develop Tests, Functio...

Key Skills and Responsibilities: IP verification Using SV/UVM or SOC Verification using C/SV VIP Integration Interconnect Protocols: AHB, AXI, APB SOC Interfaces: GPIO, SPI, I2C, UART (3+) High Speed Serial Interfaces: PCIe Gen 3/4 or USB or MIPI or UPF or DDR Coverage Closure: Code, Functional and Toggle Tools: Synopsys VCS or Cadence Incisive Technical Documentation: Testbench Specification, Test Plan Specification Good exposure to Scripting skills like Perl or Python or Shell or TCL Bachelors in Electronics Engineering is a minimum requirement Masters in Electronics or Computer Science Engineering is an added advantage 5 to 15 years minimum Exposure to working in multi-national environmen...

Position: Sr.Design Verification Engineer-Lead and above Experience: 5+ years to 30 years Location - Bangalore/Hyderabad Notice period: immediate to 30 days most preferable. Position Description: To be part of a highly skilled ASIC Team working on the newest technology nodes Responsible for overall IP verification from test plan creation, UVM development to signoff. Pair with similar domain specialists across other geographical locations on core technical initiatives SKILLS required: Good knowledge of System Verilog TB, UVM Methodology, Debug and VIP Development Exposure of SERDES/UNIPRO/PCIE/UFS/DDR protocols is an advantage Exposure to verification of complex high speed PHY Proven track re...

Job Description: We're looking for a verification SME, responsible for the SoC verification process and designing the next-generation HBM DRAM products. Deep understanding of SoC Verification, testbench architecture, SoC verification methodologies, and 2.5D & 3D package integration. Responsibilities: • Develop test plans at SOC Level and analyze Coverage. • Build verification environments to verify complex SOCs. • Develop Random/Directed test in RTL and GLS environments. • Review architectural specifications to ensure high quality. • Work with customers to understand their verification &validation requirements • Debug and identify root causes and solutions for pre-silicon and post-silicon is...

InnoPhase Inc., DBA GreenWave Radios, is at the forefront of innovation in Open RAN digital radios. Our cutting-edge solutions, powered by the Hermes64 RF SoC, are designed to enhance network energy efficiency while dramatically reducing operational expenses, with purpose-built silicon that is the heart of ORAN-based active antenna arrays. Based in San Diego, California, GreenWave Radios has earned a reputation for delivering power-efficient digital-to-RF solutions. Our commitment to innovation is backed by a robust team of more than 100 talented engineers spread across four R&D facilities worldwide and an extensive portfolio of over 120 global patent filings, underscoring our dedication to ...

We are looking for a seasoned Senior Design Verification Engineer with 8+ years of experience in verifying complex digital IPs and SoCs. The ideal candidate will have strong expertise in developing UVM-based verification environments and driving functional coverage closure. Key Responsibilities: Develop and maintain constrained-random and directed testbenches using System Verilog/UVM Define verification plans and test strategies based on specifications Write test cases, checkers, and functional coverage models Perform RTL simulations, debug failures, and ensure coverage closure Collaborate with RTL, DV, and firmware teams across verification lifecycle Support gate-level simulation, regressio...

Roles & Responsibilities: • To be part of a highly skilled ASIC Team working on the newest technology nodes • Responsible for overall IP/Block and sub-system verification from test plan creation, SystemVerilog/ UVM testbench development to signoff • Ensure first pass product through multi-dimensional verification coverage including mixed mode verification • Mentoring and coaching junior team members • Pair with similar domain specialists across other geographical locations on core technical initiatives Skills required: • Should have expertise in IP/Block/Subsystem level verification and AMBA protocols-APB/AHB/AXI. • Proven track record of building test plan, UVM Environment and test benches ...

B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Engineering. Expertise in execution and debugging of test-suites at the GPU sub-system level Expertise in GLS (Gate-Level Simulation) Expertise in writing assertions and test benches using system verilog Expertise in UVM methodologies Expertise in Test planning Expertise in sub-system level DV

Design Verification Engineer (5+ Years) Responsibilities: Develop, enhance, and maintain verification environments and testbenches using System Verilog and UVM. Create test plans from design specifications and contribute to coverage-driven and metric-driven verification goals. Build and integrate UVM components such as agents, monitors, scoreboards, sequencers. Write, debug, and automate tests to verify complex RTL modules/IP blocks; perform test regression and analyse results. Implement and analyse functional and code coverage metrics for quality signoff. Work closely with design, software, and architecture teams for feature coverage and bug resolution. Document verification results, covera...

HI All, Immediate hiring for VLSI Engineers for below location DV - SOC - BLR Location ( DDR, Ethernet) DV - Ip - HYD Location ( Pcie, Ethernet, DDR)

Expertise in Digital Verification Expertise in MAC Protocol: USB, WiFi , Bluetooth , PCIe Expertise in SOC / IP Verification Expertise in working on system Verilog assertions & test benches Expertise in working on OVM / UVM / VMM based verification flow Good knowledge in gate-level simulation, and Scripting languages like Python, TCL Must be a resident of India, preferably in Bangalore or Pune

Dear Candidate We have immediate job openings for Design verification openings Exp : 3-10 years Location : Bangalore NP : less than 45 days Job details : Develop and maintain UVM-based verification environments. Define and review verification test plans with architecture and design teams. Perform design verification using directed and constraint-random tests. Maintain regression runs and debug test failures with designers. Report and analyze verification coverage metrics. Drive verification to achieve full coverage goals. Own verification of IP blocks, sub-systems, and top-level environments. Thanks Gayathri

Dear Candidate We have immediate job openings for Design verification openings Exp : 3-10 years Location : Bangalore NP : less than 45 days Job details : Develop and maintain UVM-based verification environments. Define and review verification test plans with architecture and design teams. Perform design verification using directed and constraint-random tests. Maintain regression runs and debug test failures with designers. Report and analyze verification coverage metrics. Drive verification to achieve full coverage goals. Own verification of IP blocks, sub-systems, and top-level environments. Thanks Gayathri