PD Engineer 7Rays Semiconductors India Private Limited

3.0 - 7.0 years

0 Lacs

karnataka

On-site

As a Physical Design Engineer based in Bangalore, India with over 3 years of experience, you will be responsible for various aspects of physical design for SoC using Innovus. Your key responsibilities will include floorplanning, IO ring creation, understanding ESD and latch-up requirements for foundry, and implementation strategies for placement. You will need to demonstrate expertise in hierarchical design implementation, including partitioning, push down methodologies, core/tile PG creation, and knowledge of analog components placement based on design specifications. Additionally, RDL knowledge and experience working with packaging are essential for SoC floorplan design. A critical aspect of your role will involve PV clean-up on the floorplan and ensuring compliance with Physical Verification, ESD, foundry, and analog requirements. Deep scripting knowledge is a prerequisite for this position, along with strong problem-solving capabilities, proactive attitude, hardworking nature, and excellent interpersonal skills. To qualify for this role, you must hold a Bachelor's Degree in Electrical, Electronics, or Computer Engineering. If you are looking to leverage your experience and skills in physical design within a dynamic and innovative environment, this opportunity is tailored for you.,

Posted 1 week ago

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Senior Physical Design Lead Engineer ACL Digital

8.0 - 12.0 years

0 Lacs

karnataka

On-site

You should be a PNR Lead with over 8 years of experience, based in Bangalore. Your role will involve handling Full chip PnR tasks such as timing, congestion, and CTS issues, with an understanding of IO ring, package support, and multi-voltage design. It is crucial to have a deep understanding of synthesis, place & route, CTS, timing convergence, IR/EM checks, and signoff DRC/LVS closure. Your responsibilities will include independently planning and executing all aspects of physical design, such as floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, and DFM. You must have experience participating in all design stages including floor planning, placement, CTS, routing, physical verification, and IREM. Furthermore, your expertise should cover timing closure methodologies, DRC, LVS, ERC, and PERC rule files for lower tech node layout verification. Experience in lower tech nodes (<7nm) is required, along with strong automation skills in PERL, TCL, and EDA tool-specific scripting. You should be capable of taking complete ownership of a Block/sub-system throughout the execution cycle and possess out-of-the-box thinking to meet tighter PPA requirements.,

Posted 1 month ago

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