11 Io Design Jobs

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today's needs and tomorrow's next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we're living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globa...

The ideal candidate is a self-motivated, multi-tasker, and demonstrated team-player. You will be a Technical lead for design and development of our application specific I/O interface solutions. You should excel in working with multiple stakeholders to technically drive the project and have outstanding communication and leadership skills. Job Description In your new role you will: Technically Own complete design & development of IO library designs including both FE and BE designs. Lead interaction with system architects of product development to close IO specifications & requirements. Technically drive a cross functional team of circuit , layout , behavioral modelling and characterization eng...

As a Senior Engineer, Signal Integrity at Micron Technology, you will be a part of the Signal Integrity Research and Development (SI R&D) group, focusing on analyzing end-to-end systems solutions for various product developments. Your key responsibilities will include: - Working on various aspects of SI and PI for high-speed interfaces, including modeling and analysis for SI and PI electrical performance evaluation of Micron products - Collaborating with global teams for development and optimization of methodologies for modeling and analysis - Representing the SI R&D team in technical cross-functional collaborative groups - Supporting FAE, applications engineers with models for service to ex...

As an Analog Circuit Design professional at Cadence, you will play a critical role in shaping the world of technology. With 2+ to 8 years of experience, your expertise will be utilized in our Hyderabad office. Your educational background should include a BE/B Tech/ME/M Tech/MS degree, and a deep understanding of high-speed Serdes/Memory interface circuits such as I/Os, PLLs, Clocking, and Datapaths is essential. Your hands-on experience with PCIe Gen3/4/5/6, GDDRx/DDRx/LPDDRx memory interface circuits will be highly valued. Proficiency in Analog Design, I/O Design fundamentals, and knowledge of ESD/Reliability/SI/PI is crucial. You will be expected to lead complex IPs, manage cross-functiona...

About the Role We are seeking a highly skilled Lead IO Design Engineer with strong expertise in designing and developing high-performance Input/Output (IO) circuits. In this role, you will lead a team of engineers, drive architecture discussions, ensure design quality, and collaborate closely with cross-functional teams to deliver world-class IO solutions for cutting-edge semiconductor products. Key Responsibilities Lead the design and development of IO circuits for high-speed, low-power semiconductor devices. Define architecture , specifications , and performance targets for IO interfaces. Drive schematic design , circuit simulations , and layout reviews . Collaborate with analog/mixed-sign...

As a Sr. Signal & Power Integrity Engineer at AjnaLens in Thane (Maharashtra-India), you will be an integral part of the Electronics R&D team. We are seeking highly motivated individuals who thrive in a dynamic team environment. The ideal candidate will possess a diverse skill set and be driven to solve complex problems with simple solutions. Your primary focus will be on designing and simulating high-speed signal interfaces and power distribution networks for advanced SoC packages, interfaces such as USB 3.0, MIPI CSI-2, MIPI DSI-2, LPDDR3/LPDD4/LPDDR5, PCIe, and eMMC, as well as PCBs. Your daily tasks will include simulating, testing, and evaluating new designs to ensure compliance with El...

Roles & Responsibilities : Hands on experience in developing Analog Layout / IO layout design. Good exposure on FinFet layouts in lower nodes. Expertise in using the best and latest features of Cadence and Calibre DRC/LVS. Good exposure on ESD, LUP, antenna layout challenges and analysing/fixing EMIR issues. Capable of working independently and with team and getting work done. The ability to work communicate effectively with global engineering teams.Able to handleAnalog Layout Design, EDA Tools, DRC, LVS, Calibre, FinFet Secondary Skills Knowledge in Cadence, Virtuoso, Physical verification.

Build your career with Sykatiya Technologies. Sykatiya Technologies values Technical Ability and the positive Attitude of its highly talented team, which is evident in their contributions to customer projects. The team consists of skilled engineers and experts specializing in Design Verification, DFT/Test, Physical Design, and Analog Design for ASICs. We are currently seeking an experienced IO Design professional with 3-8 years of experience to join our team in Bangalore. The ideal candidate should have a proven track record of leading a team in the development of at least one IO library from specification to GDS. In addition, the candidate should possess a strong understanding of all collat...

You should have a minimum of 10-14 years of experience along with a strong educational background in BE/ B Tech/ ME/ M Tech / MS. Your responsibilities will include an in-depth understanding and hands-on experience in high-speed Serdes/Memory interface circuits such as I/Os, PLLs, Clocking, Datapaths, PCIe Gen3/4/5/6, GDDRx/DDRx/LPDDRx memory interface circuits. It is essential to have exposure to high-speed analog circuit design, high-speed Tx-Rx designs, and high-speed Phy architecture. Additionally, you should possess strong Analog Design and I/O Design fundamentals with knowledge of ESD/Reliability/SI/PI. You will be required to lead complex IPs, manage cross-functional dependencies, and...

You will be part of ACE India, in the P-Core design team driving Intel's latest CPUs in the latest process technology. As a member of the team, you will lead the design analysis and methodologies of various memory blocks, ensuring they meet over 5GHz frequency and low-power digital designs with optimal area utilization. Your role will involve a deep understanding of different memory design concepts such as SRAM, RF, and ROM along with expertise in static timing analysis concepts. Close collaboration with Layout and Floor planning teams will be essential for successful back end design implementation of new features. Additionally, you will specialize in memory post-silicon analysis and possess...

• Drive Area estimation, Floor Planning, Placement, Routing, Power planning, Verification, EMIR, ESD-LUP Verification & Tape out. • Understanding of low parasitic, high frequency design techniques. • Finfet process & Lower nodes; 2nm/3nm/5nm/7nm Required Candidate profile • Exp with Cadence (Virtuoso), Synopsys (CC), Calibre & ICV verification tools like LVS, DRC, Extraction. • Debugging/fixing LVS/DRC errors • Experience with EMIR, PERC tools. • Skill/TCL scripting.