5 Io Design Jobs

Roles & Responsibilities : Hands on experience in developing Analog Layout / IO layout design. Good exposure on FinFet layouts in lower nodes. Expertise in using the best and latest features of Cadence and Calibre DRC/LVS. Good exposure on ESD, LUP, antenna layout challenges and analysing/fixing EMIR issues. Capable of working independently and with team and getting work done. The ability to work communicate effectively with global engineering teams.Able to handleAnalog Layout Design, EDA Tools, DRC, LVS, Calibre, FinFet Secondary Skills Knowledge in Cadence, Virtuoso, Physical verification.

Build your career with Sykatiya Technologies. Sykatiya Technologies values Technical Ability and the positive Attitude of its highly talented team, which is evident in their contributions to customer projects. The team consists of skilled engineers and experts specializing in Design Verification, DFT/Test, Physical Design, and Analog Design for ASICs. We are currently seeking an experienced IO Design professional with 3-8 years of experience to join our team in Bangalore. The ideal candidate should have a proven track record of leading a team in the development of at least one IO library from specification to GDS. In addition, the candidate should possess a strong understanding of all collateral views, their quality assurance, and be capable of reviewing collaterals effectively. The successful candidate will be responsible for guiding the layout team on design constraints and conducting layout reviews. Experience working on FinFET nodes and a solid understanding of reliability concepts such as Aging, HCI, BTI, and EOS are essential for this role. Proficiency in IO ring level considerations including supply sequencing, ESD, SSO/SSI, R-bus, supply-to-power pad ratio, and jitter analysis is also required. The candidate should have the ability to lead the project effectively, demonstrating strong leadership skills and technical expertise. If you are a motivated and experienced IO Design professional looking to take on new challenges and make a significant impact, we encourage you to apply for this exciting opportunity at Sykatiya Technologies.,

You should have a minimum of 10-14 years of experience along with a strong educational background in BE/ B Tech/ ME/ M Tech / MS. Your responsibilities will include an in-depth understanding and hands-on experience in high-speed Serdes/Memory interface circuits such as I/Os, PLLs, Clocking, Datapaths, PCIe Gen3/4/5/6, GDDRx/DDRx/LPDDRx memory interface circuits. It is essential to have exposure to high-speed analog circuit design, high-speed Tx-Rx designs, and high-speed Phy architecture. Additionally, you should possess strong Analog Design and I/O Design fundamentals with knowledge of ESD/Reliability/SI/PI. You will be required to lead complex IPs, manage cross-functional dependencies, and mentor junior engineers. Excellent written and verbal communication skills along with problem-solving abilities are a must. Prior experience in working on cutting-edge technology nodes like 16nm/10nm/12nm/7nm would be an added advantage.,

You will be part of ACE India, in the P-Core design team driving Intel's latest CPUs in the latest process technology. As a member of the team, you will lead the design analysis and methodologies of various memory blocks, ensuring they meet over 5GHz frequency and low-power digital designs with optimal area utilization. Your role will involve a deep understanding of different memory design concepts such as SRAM, RF, and ROM along with expertise in static timing analysis concepts. Close collaboration with Layout and Floor planning teams will be essential for successful back end design implementation of new features. Additionally, you will specialize in memory post-silicon analysis and possess a good grasp of statistical variation. To qualify for this position, you must hold a master's degree in electrical or computer engineering with a minimum of 8 years of experience in the related field. Alternatively, a bachelor's degree with at least 10 years of experience will be considered. Technical expertise in synthesis, P and R tools is preferred for this role. Preferred qualifications include experience in digital design with a focus on high speed and low power, familiarity with Verilog/VHDL, and proficiency in Tcl, Perl, and Python scripting. A good understanding of spice simulations and analysis, custom circuit design, IO design, full chip clocking, and strong verbal and written communication skills are also desired. Previous experience in design and verification of high-speed clocks, hierarchical designs, and budgeting of latencies and skews will be beneficial. This role falls under the Experienced Hire category and is based in India, Bangalore. The Client Computing Group (CCG), responsible for driving business strategy and product development for Intel's PC products, is the primary business group for this position. CCG focuses on delivering purposeful computing experiences across various form factors such as notebooks, desktops, 2 in 1s, and all in ones, aiming to unlock people's potential through innovative products. The role will involve collaborating with industry partners to design and deliver a predictable cadence of leadership products, contributing to Intel's mission of enriching the lives of every person on earth. This role will be eligible for a hybrid work model, allowing employees to split their time between working on-site at the assigned Intel site and off-site. Please note that job posting details such as work model, location, or time type are subject to change.,

• Drive Area estimation, Floor Planning, Placement, Routing, Power planning, Verification, EMIR, ESD-LUP Verification & Tape out. • Understanding of low parasitic, high frequency design techniques. • Finfet process & Lower nodes; 2nm/3nm/5nm/7nm Required Candidate profile • Exp with Cadence (Virtuoso), Synopsys (CC), Calibre & ICV verification tools like LVS, DRC, Extraction. • Debugging/fixing LVS/DRC errors • Experience with EMIR, PERC tools. • Skill/TCL scripting.