ABOUT THE ROLE InCore is looking for an experienced and self-driven Field Application Engineer (FAE) to serve as a key interface between our internal product teams and external customers. This is a high-ownership role, ideal for professionals who thrive at the intersection of deep technical expertise and customer engagement. As a Senior FAE, you will lead technical integration efforts, solve c omplex customer issues, and play a vital role in growing InCore\u2019s footprint across global semiconductor clients. You wil l also mentor junior FAEs and help shape the technical customer success function at InCore. KEY RESPONSIBILITIES Solution Architecture & Technical Enablement Master InCore\u2019s Core Generation Methodology and guide customers in integrating custom core IPs into their SoCs. Lead customer discussions with engineering and leadership teams (CTOs, architects, design leads) to architect solutions aligned with business needs. Build technical collateral including app notes, demo setups, and proof-of-concept designs tailored to customer use cases. Proactively identify opportunities for expanding the use of InCore\u2019s products within customer roadmaps. Integration & Delivery Own technical delivery and post-sales integration of InCore IP in customer SoCs. Lead debugging, validation, and performance-tuning efforts on customer hardware and simulation platforms. Create and maintain scripts, sample code, and automated flows to simplify customer adoption. Manage technical escalations, coordinate with internal teams, and ensure high-quality, timely issue resolution. Customer Success & Relationship Management Act as the senior technical point-of-contact for key customer accounts. Mentor junior FAEs and help institutionalize customer engagement processes. Work closely with Sales and Product teams to convert feedback into roadmap inputs. Internal Advocacy & Process Improvement Document key learnings and use them to refine customer engagement playbooks \u200b Support pre-sales efforts by participating in technical pitches and evaluations. Identify recurring issues and contribute to tooling and automation initiatives. Requirements Deep understanding of SoC architecture, RTL design, and IP integration flows. Proficiency with Linux, shell scripting, and Python; Embedded C is a plus. Hands-on experience with debugging tools, simulation environments, and waveform viewers. Familiarity with RISC-V ISA and relevant toolchains is preferred. Excellent interpersonal, communication, and project management skills. Ability to handle customer escalations with composure and provide proactive resolutions. ELIGIBILITY CRITERIA 3\u20135 years of relevant experience in Field Applications, Pre-Sales, or Customer Engineering roles in semiconductor or EDA domains Bachelor\u2019s or Master\u2019s degree in ECE, EE, CS, or related field. Demonstrated interest in semiconductor IP, verification, or architecture. Bonus: Prior work with RISC-V-based systems. Benefits PERKS AND CULTURE High ownership in a customer-facing, technically hands-on role. Direct collaboration with InCore\u2019s founding and technical leadership. Work on Indias leading RISC-V IP platforms. Exposure to fast-paced product development and iteration cycles. Be part of the India semiconductor story from the frontlines.
We are seeking a motivated and technically skilled intern (2 positions) to lead the transformation of our existing RISC-V Application Profiler into a comprehensive trace analysis suite equivalent to ARMs Tarmac Trace Utilities. This role combines systems programming, performance analysis, and benchmark development to create next-generation profiling tools for RISC-V processors. Key Responsibilities Phase 1 (4-6 months): RISC-V Profiler Enhancement Add interactive trace browsing capabilities Develop function call tree analysis Create multiple output formats (flame graphs, histograms, etc) Phase 2 (3-4 months): Microbenchmark Framework Build automated benchmark decomposition tools On-board new benchmark suits into our existing CI/CD framework Extract microbenchmarks from standard suites (CoreMark, SPEC CPU, etc) Develop pattern recognition for performance-critical code Create validation framework Phase 3 (1-2 months): Integration & Testing Comprehensive testing and documentation Performance validation Required Skills Languages: Python, C/C++, RISC-V Assembly (mandatory) Knowledge: Computer architecture, RISC-V, performance analysis Experience: Systems programming, profiling tools, benchmarking Deliverables Enhanced RISC-V profiler with ARM Tarmac-equivalent features 50+ validated microbenchmarks from standard benchmark suites Automated benchmark decomposition framework Complete documentation and user guides Requirements Enrolled in / recently graduated from a Bachelor, Masters or PhD program in Computer Engineering, Computer Science, Electrical Engineering, or a related technical discipline. Strong programming fundamentals in C/C++ and Python. Strong RISC-V fundamentals and Computer Architecture. Ability to work 30-40 hours per week for a minimum of 24-weeks, 36-48 weeks preferable. Benefits This role offers unique exposure to the growing RISC-V ecosystem and potential for full-time conversion based on performance.