Mixed Signal Verification Texas Instruments

1.0 - 5.0 years

0 Lacs

karnataka

On-site

The ideal candidate for this position should have 1-2 years of experience in AMS design verification. You will be responsible for developing Verilog/VerilogA/VerilogAMS models for signal and power management modules to support top-level verification. Experience in full chip DV would be an added advantage. You will contribute to the development of the Full-Chip AMS-DV plan and own significant pieces of this verification process. It is essential to have the ability to drive best practices in the field of AMS-DV. In this role, you will work independently to identify bugs and resolve them formally with cross-functional teams. An understanding of analog power IPs will be beneficial as it can help in the debugging of chip-level AMS bugs. Proficiency in using tools such as Cadence Virtuoso, Spectre & Spice simulation, Incisive, and AMS simulators is required. You will utilize RTL and Gates+SDF, including process variation in back-annotated timing simulations. This will involve verifying chip-level timing between analog and digital circuits, parasitic resistance and capacitance, and using Assura parasitic extraction tools. Experience in constrained-random stimulus and auto-checking verification environments, especially constrained-random analog stimulus, is desired. The successful candidate should be able to work efficiently in a fast-paced product development environment. You will manage bug tracking and RTL code coverage, collaborate with design and systems teams to address bugs as they arise, and review digital and analog designs to provide guidance on Design for Verification architecture and features during chip development.,

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Soc Verification Engineer Coventine Digital

7.0 - 12.0 years

6 - 16 Lacs

Bengaluru

Work from Office

Key Responsibilities: Develop and execute comprehensive verification plans for SoC and NoC systems Design and maintain test benches using SystemVerilog and UVM Perform functional, performance, and low-power verification Debug and resolve design/verification issues independently Work with high-speed protocols such as AXI, CHI, PCIe, Ethernet, CXL, and UCIe Ensure thorough coverage and compliance with design specifications Collaborate with cross-functional teams including RTL, DFT, and architecture Required Skills: 7+ years of hands-on experience in SoC/NoC verification Strong expertise in System Verilog, UVM, and scripting (Python/Perl/TCL) Experience with simulation tools like VCS, Questa, or Incisive Solid understanding of interconnect protocols: AXI, CHI, PCIe, Ethernet, etc. Familiarity with coverage analysis and debugging tools Strong analytical and problem-solving skills Preferred: Experience with CXL or UCIe protocols Exposure to formal verification or emulation tools is a plus

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