92 Ic Jobs - Page 4

We are seeking a talented and detail-oriented Physical Backend Design Engineer to join our IC (Integrated circuit) development team. The role involves key aspects of physical design, including automated place and route, floorplanning, clock tree synthesis (CTS), static timing analysis (STA), power analysis, and physical verification (DRC/LVS). The ideal candidate will have a strong knowledge of physical design methodologies, experience with industry-standard tools, and a passion for delivering high-quality semiconductor solutions. You have: Bachelor s Degree in Electrical Engineering, Computer Engineering, or a related field (Master s preferred) 3+ years of experience in physical backend design for ICs. Complex chip designs through all stages of physical implementation Experience with tape-out of designs for advanced nodes is highly desirable Strong knowledge of physical design concepts, including place and route (PnR), clock tree synthesis (CTS), static timing analysis (STA) and power grid design Experience with physical verification tools like Cadence Pegasus or Mentor Calibre Familiarity with parasitic extraction tools (e.g., StarRC, Quantus, Calibre xRC) Scripting skills in Python, Tcl, Perl, or Shell for automation Required Tools: Cadence Innovus, Cadence Quantus, Cadence Tempus, Cadence Pegasus suite It would be nice if you also had: Experience with advanced process nodes (e.g., 7nm and below) Knowledge of low-power design techniques, such as multi-Vt, multi-Vdd, or clock gating Familiarity with DFT concepts and tools, Chip packaging and thermal analysis considerations, FinFET technology and 3D IC design methodologies Perform floorplanning, partitioning, and optimization to achieve area, power, and performance targets. Execute automated place and route (PnR) using industry-standard tools to generate physical layouts. Implement clock tree synthesis (CTS), ensuring low skew and efficient clock distribution. Conduct static timing analysis (STA) to verify timing closure and ensure the design meets performance requirements. Perform power analysis, including IR drop and electromigration (EM) checks, to optimize power distribution networks. Conduct physical verification tasks, including design rule checks (DRC) and layout vs. schematic (LVS) checks, to ensure manufacturability and compliance with foundry standards. Collaborate with design, verification, and DFT teams to resolve physical design challenges and improve chip performance. Work closely with foundry teams to address process technology issues and implement best practices.

We are seeking a talented and detail-oriented Physical Backend Design Engineer to join our IC (Integrated circuit) development team. The role involves key aspects of physical design, including automated place and route, floorplanning, clock tree synthesis (CTS), static timing analysis (STA), power analysis, and physical verification (DRC/LVS). The ideal candidate will have a strong knowledge of physical design methodologies, experience with industry-standard tools, and a passion for delivering high-quality semiconductor solutions. You have: Bachelor s Degree in Electrical Engineering, Computer Engineering, or a related field (Master s preferred) 3+ years of experience in physical backend design for ICs. Complex chip designs through all stages of physical implementation Experience with tape-out of designs for advanced nodes is highly desirable Strong knowledge of physical design concepts, including place and route (PnR), clock tree synthesis (CTS), static timing analysis (STA) and power grid design Experience with physical verification tools like Cadence Pegasus or Mentor Calibre Familiarity with parasitic extraction tools (e.g., StarRC, Quantus, Calibre xRC) Scripting skills in Python, Tcl, Perl, or Shell for automation Required Tools: Cadence Innovus, Cadence Quantus, Cadence Tempus, Cadence Pegasus suite It would be nice if you also had: Experience with advanced process nodes (e.g., 7nm and below) Knowledge of low-power design techniques, such as multi-Vt, multi-Vdd, or clock gating Familiarity with DFT concepts and tools, Chip packaging and thermal analysis considerations, FinFET technology and 3D IC design methodologies Perform floorplanning, partitioning, and optimization to achieve area, power, and performance targets. Execute automated place and route (PnR) using industry-standard tools to generate physical layouts. Implement clock tree synthesis (CTS), ensuring low skew and efficient clock distribution. Conduct static timing analysis (STA) to verify timing closure and ensure the design meets performance requirements. Perform power analysis, including IR drop and electromigration (EM) checks, to optimize power distribution networks. Conduct physical verification tasks, including design rule checks (DRC) and layout vs. schematic (LVS) checks, to ensure manufacturability and compliance with foundry standards. Collaborate with design, verification, and DFT teams to resolve physical design challenges and improve chip performance. Work closely with foundry teams to address process technology issues and implement best practices.

We are seeking a talented and detail-oriented Physical Backend Design Engineer to join our IC (Integrated circuit) development team. The role involves key aspects of physical design, including automated place and route, floorplanning, clock tree synthesis (CTS), static timing analysis (STA), power analysis, and physical verification (DRC/LVS). The ideal candidate will have a strong knowledge of physical design methodologies, experience with industry-standard tools, and a passion for delivering high-quality semiconductor solutions. You have: Bachelor s Degree in Electrical Engineering, Computer Engineering, or a related field (Master s preferred) 3+ years of experience in physical backend design for ICs. Complex chip designs through all stages of physical implementation Experience with tape-out of designs for advanced nodes is highly desirable Strong knowledge of physical design concepts, including place and route (PnR), clock tree synthesis (CTS), static timing analysis (STA) and power grid design Experience with physical verification tools like Cadence Pegasus or Mentor Calibre Familiarity with parasitic extraction tools (e.g., StarRC, Quantus, Calibre xRC) Scripting skills in Python, Tcl, Perl, or Shell for automation Required Tools: Cadence Innovus, Cadence Quantus, Cadence Tempus, Cadence Pegasus suite It would be nice if you also had: Experience with advanced process nodes (e.g., 7nm and below) Knowledge of low-power design techniques, such as multi-Vt, multi-Vdd, or clock gating Familiarity with DFT concepts and tools, Chip packaging and thermal analysis considerations, FinFET technology and 3D IC design methodologies Perform floorplanning, partitioning, and optimization to achieve area, power, and performance targets. Execute automated place and route (PnR) using industry-standard tools to generate physical layouts. Implement clock tree synthesis (CTS), ensuring low skew and efficient clock distribution. Conduct static timing analysis (STA) to verify timing closure and ensure the design meets performance requirements. Perform power analysis, including IR drop and electromigration (EM) checks, to optimize power distribution networks. Conduct physical verification tasks, including design rule checks (DRC) and layout vs. schematic (LVS) checks, to ensure manufacturability and compliance with foundry standards. Collaborate with design, verification, and DFT teams to resolve physical design challenges and improve chip performance. Work closely with foundry teams to address process technology issues and implement best practices.

Post Silicon Validation Engineer Experience3 to 5 Years QualificationB.E / B. Tech / M.E / M. Tech Essential Duties & Responsibilities: Experience in silicon lab validation for power management ICs. Experience with validation of Mixed-signal ICs. Experience in validation test planning, test development, execution, debug and report preparation. Hands-on experience of using lab equipment such as oscilloscope, signal analyzer, signal generator, etc. familiarity of programming and scripting languages like Python, Perl Experience in automation using NI Labview is an advantage Understanding of power management ICs, architecture, specifications interpretation is required Debug skills to zero in on an issue, coordination with cross-functional teams is required Skills Experience LabVIEW, PMIC, Post Silicon Validation, System Validation, Testing Validation Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore USATexas Location - Bengaluru,Chennai,Hyderabad,Noida

Who We Are Applied Materials is the global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service cutting-edge equipment that helps our customers manufacture display and semiconductor chips- the brains of devices we use every day. As the foundation of the global electronics industry, Applied enables the exciting technologies that literally connect our world- like AI and IoT. If you want to work beyond the cutting-edge, continuously pushing the boundaries of"science and engineering to make possible"the next generations of technology, join us to Make Possible® a Better Future. What We Offer Location: Bangalore,IND At Applied, we prioritize the well-being of you and your family and encourage you to bring your best self to work. Your happiness, health, and resiliency are at the core of our benefits and wellness programs. Our robust total rewards package makes it easier to take care of your whole self and your whole family. Were committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Learn more about our benefits . Youll also benefit from a supportive work culture that encourages you to learn, develop and grow your career as you take on challenges and drive innovative solutions for our customers."We empower our team to push the boundaries of what is possible"”while learning every day in a supportive leading global company. Visit our Careers website to learn more about careers at Applied. About Applied Applied Materials is the leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. Our expertise in modifying materials at atomic levels and on an industrial scale enables customers to transform possibilities into reality. At Applied Materials, our innovations make possible the technology shaping the future. Applied Materials India is looking for an Application Engineer to join our team on Yi eld Technology Group ( YTG ). YTG is an innovative platform that develops and produces high-precision electron optical devices (electron microscopes) and advanced test systems utilizing e-beam technology for display and semiconductor advanced packaging industry. YTG is working in an internationally networked setup, with system platform design and e-beam technology development being aligned between multiple development sites located in Germany, Taiwan, and India, and with its manufacturing located in Taiwan and Germany (but with a global sourcing approach), to best serve our customers located in Asia, the USA and Europe." Roles and Responsibility Understand and translate market requirement to product spec ifications. Work with algorithm, system, software and other cross functional teams to analyze alternative solutions and provide data for decision making. Tool performance with gap/ limitation analysis to create new methodologies in order to optimize system performance for specific application . Support customer & field issues driving demos and adoption of developed tools/ features. Qualifications Master/Integrated Dual Degree/PhD scholars from premier academic institutions with 2-4 years experience, specialization in Materials Engineering/Microelectronics/Chemical Engineering/Engineering Physics / Mechatronics Our Ideal Candidate Sound fundamentals of semiconductor device physics and process knowledge (deposition, etching, etc.) Requires 70% travel on short notice to leading semiconductor chip manufacturing fabs overseas and Applied Materials headquarters Detail oriented, with strong analytical skill, problem solving and excellent communication skills, strive to get to the deep technical details Collaborate with cross-functional teams, strong documentation and presentation skill. Additional Qualifications F amiliarity of working in a semiconductor fab and experience in interfacing with field support engineers is highly desirable. Understanding of Metrology process and requirements in IC manufacturing is highly desirable. Good programming skills and hands on experience in Python. ML/DL knowledge will be an advantage. Additional Information Time Type: Full time Employee Type: Assignee / Regular Travel: Yes, 25% of the Time Relocation Eligible: Yes Applied Materials is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law.

Project Role : Engineering Services Practitioner Project Role Description : Assist with end-to-end engineering services to develop technical engineering solutions to solve problems and achieve business objectives. Solve engineering problems and achieve business objectives using scientific, socio-economic, technical knowledge and practical experience. Work across structural and stress design, qualification, configuration and technical management. Must have skills : Manufacturing Design & Engineering Solutions Good to have skills : NAMinimum 2 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Engineering Services Practitioner, you will assist with end-to-end engineering services to develop technical engineering solutions, solve problems, and achieve business objectives. You will work across structural and stress design, qualification, configuration, and technical management, utilizing scientific, socio-economic, technical knowledge, and practical experience. Roles & Responsibilities- 3-6 Years of experience in the field of General Assembly (TCF). Experience in Digital manufacturing tools (3D Experience /DELMIA V5/Team center visualization/Human Jack/ Process Simulate/IC.IDO/Unity/VR/FAPLIS/Micro station etc.)- Assembly process planning, documentation & issue resolution - Assembly equipment design, planning, installation & commissioning- Physical ergonomic Assessment in production plant- Problem Solving & Project Management- C#/Python/Powerbi - Designing small Jigs & Fixtures- Executing new vehicle program projects.- Conduct dynamic and static clearance analysis studies for Cars using 3D Experience - Conduct ergonomic studies using 3D Experience - Virtual validation of plant tools Professional & Technical Skills: - Must To Have Skills: Proficiency in Manufacturing Design & Engineering Solutions.- Strong understanding of engineering principles and practices.- Experience in utilizing CAD software for design and analysis.- Knowledge of material selection and manufacturing processes. Additional Information:- The candidate should have a minimum of 3 years of experience in Manufacturing Design & Engineering Solutions.- This position is based at our Bengaluru office.- A 15 years full-time education is required. Qualification 15 years full time education

Role & responsibilities Job Title: Mix Signal ASIC/IC Functional safety engineer/manager Job location: Bangalore Work mode: Hybrid Mode of employment: Permanent / Direct Company Payroll OVERVIEW: Seeks a dynamic and experienced Mix Signal ASIC/IC Functional Safety Engineer & Manager to join the Sensor Global Quality Engineering Center within its Sensors Quality Organization. This role focuses on ensuring the compliance to Functional Safety requirements of sensor products from project definition to production release for Automotive and Industrial & Transportation (ICT) markets. This role will engage with various Engineering Centers of Expertise and manufacturing plant globally. It is a strategic role to support Sensor Technology roadmap based in our growing Global Design Center Bangalore India. KEY RESPONSIBILITIES: Functional Safety for New Technology Development: Ensure that functional safety requirements are met from project definition to production launch according to company stage gate procedure. Provide guidance to project stakeholders to adhere to ISO26262 standards Negotiate and mutually agree on required safety goals with customers (DAI) Contribute to the development of technical safety Concepts per ISO26262. Deliver Functional safety Work Products as per ISO26262 such as Safety Plan, HARA, FSR/C, TSR/C, FMEDA at hardware level (IP block/Gate). Review gate exits and release Functional Safety documentation (Safety Case) to enable production launch. YOU MUST HAVE Functional Safety Certification Experience: Minimum of 10 Years Experience in functional safety at hardware level SoC, ASIC, IC Successful release in production of project of at least ASIL C level . Proficiency with all Functional Safety tools from safety plan to safety case, including SPFM, LFM metrics Master FDMEA and FIT calculation Knowledge of Quality Standards: Familiarity with ISO 9001, AS 9100, IATF 16949 Strong English communication skills Customer & Leadership Engagement: Ensure efficient communication with customers and leadership team on functional safety related topics Anticipate and manage escalations effectively. Process & Continuous Improvement Management: Inspire a Zero-Defect mindset by ensuring data-driven problem-solving and improvement initiatives. Evaluate project outcomes, identify areas for improvement, and suggest enhancements to processes. WE VALUE Six Sigma Green Belt or Black Belt certification Experience in Cybersecurity ISO 27001 or ISO/SAE 21434 Experience participating to VDA audits, IATF audits EDUCATION Bachelor or Master in Engineering or related discipline Interested candidate please apply here. Also share your profile to chidananda@manpower.co.in; Best Regards, HR Team, Manpower Group Preferred candidate profile

Hi, We have a vacancy in Hyderabad for INVESTMENT SPECIALIST - Leading Bank Grade: Senior Manager or AVP CTC up to 20Lacs fixed Looking for profiles from: Sales or Investment background from banking/fund houses. Job Role: Ownership of the Investments target of the Branch Banking channel mapped to Increase the Mutual Fund AUM for the mapped Area Penetration of client base for creating new investors in MF / investments from existing client base Increase in (investments products) productivity of Phone Banking officers Acquisitions (NTB) attributed to presence of IC i.e NTB opened by officers on the back of investments due to the presence of the IC Other Key areas to be done periodically Officers training Driving business /coordinating with Sr. RCMS /National Head Client coverage / joint phone calls Portfolio construction and reviews are done periodically by self and team Training & Development for new joiners for better performance Process adherence Dynamic person who can think and implement new strategies for customer acquisition, penetration and retention. Job Requirements 8-10 years work experience in NBFC, Banks, Mutual Fund industry In depth domain knowledge of Mutual Fund investments in detail, PMS Equity Market. Current Economy Distribution / Channel management Good communication and presentation skills, Good interpersonal skills Ability to work with other people well, Willing to travel. Pro-activeness to know things and drive business and people How to Apply : EMAIL: cv to selvi.sai@upgrad.com / Whatsapp CV to 9361184170 (Or) Call me back to 9361184170 Thanks & Regards, Selvi Sai Chief Recruitment Specialist - Leadership & Mid / Senior Level Hiring m +91-9361184170 |

1. Hands on work on custom layout for analog blocks like High Speed SerDes and General purpose IO designs with Cadence Virtuoso on latest technologies like 5nm and below and also take leadership roles in delivery of IPs 2. Work on Floor planning, power design, signal routing strategy, EMIR awareness andparasitic optimisations 3. Understand and apply analog Layout techniques to ensure the design meets performance with minimum possible area and good yield. 4. Participate in building and enhancing layout flow for faster, higher quality design process. 5. Checking physical verifications like DRC/LVS/ERC/ANT/DFM and other IBM internal checks 6. Collaborate with Circuit Designers to solve challenging problems 7. Writing /PYTHON scripts to automate repetitive tasks 8. Work with Place and Route engineer to integrate custom macros into top level. 9. Able to perform design reviews across global team 10. Work closely with required global teams to ensure the success of the whole product. 11. Leadership in delivery of macros we plan to own from India Job requirements: 1. Experience in doing layouts for analog blocks like SerDes, ADCs, DACs, LDOs, PLLs, BGAP & amplifiers etc. 2. Experience in designing layouts for high-speed circuits is a plus. 3. Layout experience in the following technology nodes3nm, 5nm and 7nm FinFET. 4. Good team worker with multi-discipline, multi-cultural and multi-site environments 5. Strong fundamental knowledge in semiconductor device physics, layout principles, IC reliability and failure mechanisms 6. Good problem-solving skills are essential where problems are analysed upfront, identifying gaps, and providing optimum solutions7. Knowledge in Skill/perl/tcl/Python scripting is a plus. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise The Analog layout design engineer with experience in next generation Ultra high speed serial IO link (HSS) interface for Cognitive, ML,DL, and data center applications. The engineer needs to have knowledge in the design and development full custom analog layouts for ultra high speed 32G/50G/112G IO link interfaces. Preferred technical and professional experience Experience in 7 and 14 nm analog layout design. Working on Cutting edge technology and HSS domain . Quick learner, deep layout design knowledge, problem solving skills and good communication skills with cross teams across the Geos.

Location :- Vadodara / Kerela Post : Technical Surveyor Plant :- Service Provider Qualification :- Diploma/ BE Mechanical / Electrical /EC / IC Experience :- Fresher / Experience both can applicable Required Candidate profile Job Time :- 9am-6pm Salary :- 15,000 -20,000 CTC Facility :- No Post :- Surveyor ( 50% office work , 50 % site work ) Mo no : +91 90816 99700 / Mo No : 9081699500 / 9081699600

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Working experience (2+ years) in preferably Memory design Compiler approach of developing embedded SRAM/ROM development Fundamental know how on bit cell and its characteristics (SNM, WM, Cell current, Standby current, data retention) Fundamentals of process variability and its effect on memory design Strong understanding of Digital/Memory circuit design/layouts Critical path modeling concept, various type of models ( RC, C, Pai, ladder, distributive, etc) Good knowledge of semiconductor physics in general. Knowledge of and affinity to IC technology and IP design is mandatory Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Cloud Ops Engineer (IC)- Manager - BLR/Pun/GGN Responsibilities Building, operating, and continuously enhancing the KPMG Insight Platform (KIP) and associated supporting projects. Senior DevOps Engineer Level 2 colleagues are experienced professionals who bring deep knowledge of their discipline to both service teams or engagements. They have mastered the art of being an effective individual contributor across multiple projects or engagements either within a team setting or as an individual taking the project from inception to delivered. They are the go to person when the Lead of the engagement or overall project is away or unavailable and has the ability to steer the ship as and when required. They are the default Lead Engineer when the Lead is away or unavailable or when required and have built the respect from the client and team to do so. Understands and despises technical debt within a project or engagements and strives to eradicate where possible convincing both peers and clients of the importance. Regularly coaches and mentors engineers across all capabilities within Engineering and where possible, performance manages colleagues within same domain. A very keen contributor of sharing knowledge to various levels of skillset from technical to senior non-technical stakeholder either internally or externally, directly to clients. Contributes to open source projects or industry more generally, representing themselves and the firm. They also are heavily involved in the recruitment and hiring process of technical candidates reviewing applications, tech tests and conducting interviews. They still seek guidance from peers and seniors as well as nurturing the relationships with both internal and clients to drive brand attraction and revenue. Skills/ Qualifications Strong knowledge of Azure & M365. Ability to work on UK Gov projects. Proven team management experience. Experience of UK internal processes. Understanding of UK Advisory direction. Frequently takes on and writes higher complex cards and tasks within a team or on an engagement Has the ability to take a large problem or engagement and breakdown into achievable milestones and tasks for individual or team contribution Proficient in architecting and building Cloud Infrastructure as Code for clients Strong knowledge and skills within KPMG Core technology Regularly recognised as a highly impactful technical engineer delivering consistently high quality Ability to propose and challenge technical scope with seniors where relevant Make pragmatic trade-offs between perfection and technical debt aligning to business/client needs and priorities Demonstrates their technical skills not only in code by leading design decisions for engagements and projects Required Candidate profile Candidate Experience Should Be : 10 To 14 Candidate Degree Should Be : BE-Comp/IT,BE-Other,BTech-Comp/IT,BTech-Other,MBA,MCA

Urgently hiring for a Reputed Organization in Mobile Industry - Role - Repair Engineer (L-4) TRC Department Must have experience in PCB Repair CTC- as per company norms Interested Candidates Can direct call or whatsapp Cv - 9891066650 Madhuri Required Candidate profile Must have experience in PCB repair L4 level .

Job Area: Engineering Group, Engineering Group > Software Engineering General Summary: Qualcomm ADAS/Autonomy team is engaged in offering optimized solutions built on DSP, computer vision and machine learning algorithms for the Qualcomm ADAS/Autonomy SoCs. We are seeking engineers with experience in system and SoC SW level functional safety concepts. The job requires understanding and defining of the Safety Concept and Architecture, Software Safety requirements, defining and deploying safety processes and development of Safety software by following the ISO26262 software processes. Interaction with customers, architects and test/integration teams are required as part of the job. The job also involves working with the Software quality team for adherence of ISO26262 and ASPICE processes. In this role, the candidate will work with local and global teams to understand, define and implement and productize Automotive specific features including software enablement (drivers/BSP/RTOS/AUTOSAR MCAL), security, functional safety, and power applied to Automotive products on our current and next generation SoCs. The candidate will also have the responsibility to coordinate and execute plans which will encompass validation of all the feature requirements. The Candidate will have the responsibility to identify and address any abnormal discoveries by root-causing and providing detailed corrective actions in the form of optimizations and/or fixes. When possible, the candidate is expected to prototype and pre-validate recommended fixes. Additionally, the candidate will be responsible for any automation of design under test along with validation efforts and working closely with design/production/bench IP teams. Minimum Qualifications: "¢ Bachelor's degree in Engineering, Information Systems, Computer Science, or related field. 3-6 years of Embedded Software Development experience, including low level drivers, and RTOS The candidate should possess 3 to 6 years of industry experience in embedded software driver development and having expertise in one or more below areas would be preferred: Should be able to ramp up fast and must have the attitude to work with the team. Strong C and Assembly Programming with OS & Multi-Processor concepts Embedded software development in C and C++ on ARM or similar cores. Hands on experience of driver development on any RTOS, Experience in SafeRTOS/FreeRTOS based development is nice to have Experience in Autosar MCAL development is nice to have Experience in Autosar BSW integration and validation is nice to have ARM Trust-Zone & ARMv7/v8 architecture. Good debugging skills with experience on debugging with Lauterbach JTAG debuggers. Work on challenging customer requirements and issues. Basic understanding one or more of hardware blocks - Clocks, PLLs, GPIO, Interrupt Controllers (GIC), Peripherals (SPI/I2C/UART/CAN/Ethernet/Clock/etc) Automotive SW development experience is must have Experience in ISO26262/functional safety and ASPICE is highly desirable Basic knowledge on Power Mgmt. IC is desirable Knowledge of Software/Hardware Security concepts is desirable Closely work with the hardware team to contribute/suggest modifications to the hardware design. Any past working experience on Qualcomm chips nice to have

Role & responsibilities Job Title: Mix Signal ASIC/IC Functional safety engineer/manager Job location: Bangalore Work mode: Hybrid Mode of employment: Permanent / Direct Company Payroll OVERVIEW: Seeks a dynamic and experienced Mix Signal ASIC/IC Functional Safety Engineer & Manager to join the Sensor Global Quality Engineering Center within its TE Sensors Quality Organization. This role focuses on ensuring the compliance to Functional Safety requirements of sensor products from project definition to production release for Automotive and Industrial & Transportation (ICT) markets. This role will engage with various Engineering Centers of Expertise and manufacturing plant globally. It is a strategic role to support TE Sensor Technology roadmap based in our growing Global Design Center Bangalore India. KEY RESPONSIBILITIES: Functional Safety for New Technology Development: Ensure that functional safety requirements are met from project definition to production launch according to TE stage gate procedure. Provide guidance to project stakeholders to adhere to ISO26262 standards Negotiate and mutually agree on required safety goals with customers (DAI) Contribute to the development of technical safety Concepts per ISO26262. Deliver Functional safety Work Products as per ISO26262 such as Safety Plan, HARA, FSR/C, TSR/C, FMEDA at hardware level (IP block/Gate). Review gate exits and release Functional Safety documentation (Safety Case) to enable production launch. YOU MUST HAVE Functional Safety Certification Experience: Minimum of 10 Years’ Experience in functional safety at hardware level SoC, ASIC, IC Successful release in production of project of at least ASIL C level . Proficiency with all Functional Safety tools from safety plan to safety case, including SPFM, LFM metrics Master FDMEA and FIT calculation Knowledge of Quality Standards: Familiarity with ISO 9001, AS 9100, IATF 16949 Strong English communication skills Customer & Leadership Engagement: Ensure efficient communication with customers and leadership team on functional safety related topics Anticipate and manage escalations effectively. Process & Continuous Improvement Management: Inspire a Zero-Defect mindset by ensuring data-driven problem-solving and improvement initiatives. Evaluate project outcomes, identify areas for improvement, and suggest enhancements to processes. WE VALUE Six Sigma Green Belt or Black Belt certification Experience in Cybersecurity ISO 27001 or ISO/SAE 21434 Experience participating to VDA audits, IATF audits EDUCATION Bachelor or Master in Engineering or related discipline Interested candidate please apply here. Also share your profile to chidananda@manpower.co.in; Best Regards, HR Team, Manpower Group Preferred candidate profile

We are seeking a highly motivated and experienced Study Director to oversee chemical characterization studies within our research and development team. The ideal candidate will have a strong background in analytical chemistry, extensive knowledge of chemical characterization techniques, and a proven track record in managing complex projects. Key Responsibilities: - Lead and manage chemical characterization studies, including planning, execution, and reporting of results. - Develop study protocols and ensure compliance with regulatory guidelines and internal standards. - Coordinate and communicate with cross-functional teams. - Analyze and interpret data, preparing comprehensive reports and presentations for internal and external stakeholders. - Mentor and train junior staff in scientific techniques and best practices. - Ensure that laboratory safety protocols are followed and maintain a clean and organized work environment. - Stay current with industry trends and advancements in chemical characterization methodologies. Qualifications: - Ph.D. or equivalent degree in Chemistry, or a related field. - A minimum of 10 years of experience in chemical characterization or a similar role within a laboratory setting. - Expertise in techniques such as LCMS - QTOF, GCMS, NVR, ICPMS, IC and other relevant analytical methods. - Strong project management skills with the ability to lead multiple projects simultaneously. - Excellent communication, organizational, and problem-solving abilities. - Familiarity with regulatory requirements and guidelines in the pharmaceutical or biotechnology industry. This position offers a competitive salary and benefits package, along with opportunities for professional growth and development. If you are passionate about advancing scientific research and thrive in a collaborative environment, we encourage you to apply. Roles and Responsibilities 1. Oversee and manage chemical characterization studies from initiation to completion, ensuring adherence to regulatory standards and internal protocols. 2. Design study plans and methodologies that are scientifically sound and aligned with project objectives, including the selection of appropriate analytical techniques and equipment. 3. Coordinate with cross-functional teams, including project managers, chemists, and quality assurance personnel, to ensure effective study execution and communication. 4. Review and approve study protocols, analytical methods, and reports to ensure accuracy, compliance, and scientific integrity. 5. Provide technical expertise and guidance related to chemical characterization, including the interpretation of analytical data and results. 6. Ensure that all studies are conducted in compliance with Good Laboratory Practice (GLP) and other relevant regulations. 7. Manage study budgets and timelines, identifying potential risks and implementing mitigation strategies to ensure successful project delivery. 8. Train and mentor staff on appropriate methodologies and regulatory requirements related to chemical characterization studies. 9. Participate in project meetings, presenting study findings and progress updates to stakeholders, and incorporating feedback into study design and implementation. 10. Maintain up-to-date knowledge of industry trends, emerging technologies, and regulatory changes affecting chemical characterization and related fields. 11. Facilitate communication with regulatory agencies as needed, providing data and documentation to support submissions and inquiries. 12. Contribute to the continuous improvement of departmental processes and methodologies, ensuring best practices are followed in study design and execution.

8+ experience as Cloud Developer, should have worked on at least 2-3 implementation projects Expert in Cloud data migration of Master and Transactional data across Finance, PPM and SCM modules Should be able to device the data migration strategy, perform data migration and report the results to stakeholder Conversant in Cloud technical tools – FBL, HDL, HCM extracts, Fast formulas, BI Publisher, OTBI, Smart Views, Page Composer and Application composer Nice to have extensive experience in Cloud Integration via oracle Cloud ICS or Oracle SOA Nice to have experience in performing integrations between Cloud and 3 party applications both inbound and outbound – File based, webservice and XML based Should be conversant in documentation – Technical Design, Unit Test Scripts, Code migration document, Integration test scripts etc., Work with client/functional team to gather and analyze business requirements and prepare technical design documents. Investigate and resolve complex problems through research and technical analysis. Provide continual assessment and review of unit testing and integration plans to ensure the solutions meet the business need and are working as designed. Work with functional resources in reviewing functional specifications and translating technical issues/requests in a manner that can be understood by the business users, and vice versa. Review change management procedures and follow methodology for moving technical conversion and interface activities into production. Recommends alternate choices, trade-offs, and impact analysis. Participate in testing efforts to identify and resolve conversion and/or interface issues. Understands business requirements and works with process analysts to ensure that conversion/integration activities enhance business processes or to minimize any negative impact. Oracle Cloud Certification with Oracle university in Oracle Cloud ICS or SOA is a MUST Job Segment ERP, Oracle, Database, Developer, XML, Technology