5.0 - 9.0 years

0 Lacs

hyderabad, telangana

On-site

You should possess in-depth knowledge and hands-on experience in Netlist2GDSII Implementation, including tasks such as Floorplanning, Power Grid Design, Placement, Clock Tree Synthesis (CTS), Routing, Static Timing Analysis (STA), Power Integrity Analysis, Physical Verification, and Chip finishing. It is essential to have experience with Physical Design Methodologies and sub-micron technology, particularly in 16nm and lower technology nodes. Moreover, you should have expertise in Analog and Mixed Signal Design and be familiar with handling designs with more than 5M instance count and operating at a frequency of 1.5GHz. Proficiency in programming languages such as Tcl, Tk, and Perl is required to automate the design process and enhance efficiency. Hands-on experience with PnR Suite from Cadence & Synopsys, specifically Innovus & ICC2, is a must. Additionally, you should have a strong background in Static Timing Analysis using tools like PrimeTime for SI analysis, EM/IR-Drop analysis with PT-PX and Redhawk, as well as Physical Verification using Calibre. Understanding the practical application of methodologies, Physical Design Tools, Flow Automation, and driving improvements in these areas is highly beneficial. Experience in complex SOC integration, Low Power and High-Speed Design, as well as proficiency in Advanced Physical Verification Techniques, are desirable skills for this role.,

Posted 1 week ago

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