2.0 - 6.0 years

0 Lacs

karnataka

On-site

You have a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. You possess 3 years of experience in architecture, hardware, digital design, and software design, along with 2 years of experience in Verilog/SystemVerilog. Your experience includes knowledge in computer architecture and digital design or Internet Protocol (IP) integration such as Peripheral Component Interconnect Express (PCIe) and Double Data Rate (DDR) memory. Ideally, you hold a Master's degree in Electrical Engineering, Computer Science, or a related field and have 4 years of experience working on Field Programmable Gate Array (FPGA) platforms or Emulation platforms with Internet Protocols (IPs) like PCIe, DDR memory, Gigabit Ethernet, and Flash. You also have experience in developing architectures for Machine Learning Accelerators and in writing or debugging Verilog/Register-Transfer Level (RTL) code for ASIC/FPGA designs, with waveform debug skills and knowledge of chip design flows. As part of this role, you will contribute to shaping the future of AI/ML hardware acceleration, particularly focusing on TPU (Tensor Processing Unit) technology that drives Google's demanding AI/ML applications. You will collaborate with a diverse team to develop custom silicon solutions that power Google's TPU, innovating products enjoyed by users worldwide. Your responsibilities will involve verifying complex digital designs, especially TPU architecture integration within AI/ML-driven systems. Your tasks will include integrating hardware and software stacks for pre-silicon validation of Google Cloud Tensor Processing Unit (TPU) projects using emulation platforms, creating custom test cases and tools, and ensuring the quality of silicon bring-up, validation, and characterization programs. Additionally, you will work on debugging issues, collaborating with various teams, and contributing to the development of tools, validation firmware, and testing infrastructure for Google Cloud data center systems. Overall, your role will focus on enabling chip features through firmware and driver stack, validating hardware and software designs, designing ASIC models for Emulation/FPGA Prototypes, optimizing RTL transformations, and improving hardware modeling accuracy. You will play a key role in driving debug discussions, coordinating hardware and software deliveries, and benchmarking performance to ensure efficient operations of Google's systems.,

Posted 4 days ago

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Senior Principal Engineer - IP Design NXP Semiconductors

18.0 - 22.0 years

0 Lacs

noida, uttar pradesh

On-site

You are a highly motivated and energetic individual with a team-oriented approach, responsible for driving roadmaps in the IP/Subsystem domain. Your role involves delving deep into logic design, architecting, and developing complex IPs/Subsystems solutions. Working closely with a team of global experts in Systems and SoC Design functions, you will lead or address design/architectural challenges within the context of complex IPs and overall system level solutions. Your tasks will range from developing high-level specifications to actual design implementation. Your key responsibilities include owning and driving roadmaps for the complete IP/Subsystem domains portfolio within the global R&D team. You will perform benchmarks against other industry players to ensure differentiating features for customers with a high level of innovation. Architecting and designing complex IPs and Subsystems across various protocols required for Edge processing, Automotive Self-Driving Vehicles, In-Vehicle experience, Gateway Systems, Fail-Safe Subsystems (ASIL-D), etc., will be part of your role. You will be responsible for leading IPs/Subsystems from concept to design and development, achieving final design performance in an integrated system within aggressive, market-driven schedules. Ensuring quality adherence throughout the IP development cycle, analyzing existing processes, recommending and implementing process improvements, and driving and mentoring teams towards achieving Zero Defect designs are crucial aspects of your role. Additionally, you will be responsible for owning and driving global IP design methodologies across sites with global stakeholders. As a self-starter with over 18 years of experience, you should be able to architect and design complex IP designs/Subsystems with minimal supervision. Your expertise should include custom processor designs with key DSP functions, processor designs like RISC-V Core, cache-based subsystems, high-speed serial protocols, and associated challenges, understanding of key external memory interface protocols, microcontroller architecture, bus protocols, HDLs, scripting languages, and C/C++ for hardware modeling. Knowledge of end-to-end IP development flow, testbench and testplan development, and pre-silicon validation using FPGA/Emulation Board would be advantageous. In terms of soft skills, you should possess proficient skills in both written and verbal communication, with the ability to articulate well. Demonstrating a sense of ownership, engaging everyone with trust and respect, showcasing emotional intelligence, and embodying leadership values are essential for success in this role. You should have the ability to work effectively as part of a team, whether local, remote, or multisite.,

Posted 1 week ago

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