Silicon Validation Engineer, HBM, Google Cloud Google

5.0 - 9.0 years

0 Lacs

karnataka

On-site

As a candidate for this position, you should hold a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or possess equivalent practical experience. Additionally, you should have at least 5 years of experience in High Bandwidth Memory/Double Data Rate (HBM/DDR) technology. Your responsibilities will include silicon bringup, functional validation, characterizing, and qualification, as well as working with board schematics, layout, and debug methodologies utilizing lab equipment. Preferred qualifications for this role include experience in hardware emulation with hardware/software integration, proficiency in coding languages such as Python for automation development, and experience in Register-Transfer Level (RTL) design, verification, or emulation. Knowledge of SoC architecture, boot flows, and HBM/DDR standards will be advantageous. In this role, you will contribute to shaping the future of AI/ML hardware acceleration by working on cutting-edge TPU (Tensor Processing Unit) technology that powers Google's AI/ML applications. You will be part of a team dedicated to developing custom silicon solutions for Google's TPUs, with a focus on design and verification expertise related to TPU architecture and AI/ML-driven systems. Your primary responsibility will be the post-silicon validation of Cloud Tensor Processing Unit (TPU) projects. This will involve creating test plans and content for subsystem testing, verifying content on pre-silicon platforms, executing tests on post-silicon platforms, and debugging issues. Collaboration with engineers from various teams will be essential in validating functional, power, performance, and electrical characteristics of the Cloud TPU silicon to ensure high-quality designs for next-generation data center accelerators. The ML, Systems, & Cloud AI (MSCA) organization at Google is involved in designing, implementing, and managing hardware, software, machine learning, and systems infrastructure for Google services and Google Cloud. Your work will impact millions of users worldwide by prioritizing security, efficiency, and reliability in developing TPUs and running a global network. Your responsibilities will include developing and executing tests for memory controller High Bandwidth Memory (HBM) post-silicon validation, driving debugging efforts, ensuring validation coverage, and assisting in pre-silicon integration and validation on hardware emulators.,

Posted 4 days ago

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Silicon Design Verification Engineer, Google Cloud Google Inc

5.0 - 10.0 years

5 - 10 Lacs

Bengaluru, Karnataka, India

On-site

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 5 years of experience in High Bandwidth Memory/Double Data Rate (HBM/DDR). Experience in silicon bringup, functional validation, characterizing, and qualification. Experience with board schematics, layout, and debug methodologies with using lab equipment. Preferred qualifications: Experience in hardware emulation with hardware/software integration. Experience in coding (e.g., Python) for automation development. Experience in Register-Transfer Level (RTL) design, verification or emulation. Knowledge of SoC architecture including boot flows. Knowledge of HBM/DDR standards. Responsibilities Develop and execute tests for memory controller High Bandwidth Memory (HBM) post-silicon validation and on hardware emulators and assist in bring-up processes from prototyping through post-silicon validation. Drive debugging and investigation efforts to root-cause, cross-functional issues. This includes pre-silicon prototyping platforms as well as post-silicon bringup and production. Ensure validation provides necessary functional coverage for skilled design. Help operate and maintain our hardware emulation platform for pre-silicon integration and validation.

Posted 3 weeks ago

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Principal Application Engineer Cadence Design Systems

7.0 - 15.0 years

3 - 10 Lacs

Noida, Uttar Pradesh, India

On-site

Assume technical leadership for all virtual interface solutions for Palladium and Protium and become the go-to expert for the rest of the North America field AE team . Provide in-depth technical assistance in collaboration with RD to help support advanced emulation flows to secure design wins . Champion the customer needs and work closely with RD in India to develop competitive and creative technical solutions. Requirements Strong experience in hardware emulation with knowledge of interface protocols like PCIe , AMBA and Ethernet Experience in synthesizable coding style Knowledge of fundamental SoC Architectures Experience with SystemVerilog, VHDL, Verilog, C/C++/SystemC Ability to quickly analyze emulation environments and design complexity. Strong verbal and written communication skills, with the ability to effectively bridge communication channels between external customers, NA FAE team and internal RD teams. Strong teamwork skills 8+ years industry experience

Posted 2 months ago

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