5.0 - 10.0 years

15 - 30 Lacs

bengaluru

Work from Office

Key Responsibilities: Perform gate-level simulations (GLS) for ASIC/SOC designs post-synthesis and post-layout. Validate timing, power-up behavior, clock gating, and low-power modes (with UPF/CPF ). Develop and execute GLS test plans including functional, scan, and ATPG pattern verification. Work closely with RTL design, DFT, STA, and backend teams for issue resolution. Debug timing-related issues in post-layout netlist simulations . Ensure zero-delay and SDF-annotated simulation coverage. Requirements: Strong experience in GLS verification at the netlist level with SDF annotation. Solid understanding of timing closure , STA concepts, and simulation tools. Proficient in SystemVerilog , scrip...

Posted 19 hours ago

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