153 Gls Jobs - Page 5

Job Description: We are looking for experienced DV Lead Engineers with a strong background in SystemVerilog, UVM, and protocol-based SoC/IP verification . The ideal candidate will have excellent debugging and leadership skills, with hands-on experience in building testbenches and leading verification teams. Key Responsibilities: Build comprehensive test plans , test cases , and functional coverage from specification documents Architect and develop UVM-based testbenches and verification environments Work with high-speed protocols such as AXI, AHB, APB, PCIe Hands-on debugging and simulation using Synopsys and Cadence tools Mentor junior team members, collaborate cross-functionally, and lead p...

Job Description: We are looking for skilled Design Verification Engineers with 5-10 years of strong experience in the semiconductor domain. Ideal candidates will have hands-on experience in SystemVerilog (SV) and UVM , along with a solid understanding of SoC/IP level verification , GLS , and CPU verification . Key Skills Required: SystemVerilog (SV) UVM (Universal Verification Methodology) SoC/IP Level Verification GLS (Gate-Level Simulation) CPU/Sub-system Verification High-speed interface protocols: PCIe, DDR, Ethernet Requirements: Immediate to 30 days joiners only Willing to work from office (Bengaluru or Hyderabad) Strong debugging and problem-solving skills Excellent communication and ...

Role & responsibilities Please interested candidate send me cv :galeiah.g@honeybeetechsolutions.com Position Name DV Engineer -GLS Position type: Permanent Total Exp: 5-7 years Notice Period: Immediate to 15days Work Location: Bangalore KEY RESPONSIBILITIES: "Key Responsibilities: Develop and implement scalable UVM-based verification environments Lead and execute GLS (Gate-Level Simulation)timing-aware and glitch-sensitive validation is a core part of this role Perform Clock Domain Crossing (CDC) verification using industry-standard methodologies Collaborate cross-functionally with RTL, DFT, and system teams for end-to-end verification closure Analyze waveforms, root-cause issues, and contri...

Job Description As a member of the Design Verification [Pre-Silicon DV] Team for NXP WCS/SCE BU. You will be responsible for verification of various IPs and/or SoC. Candidate must be self-motivated and capable of working independently or as part of a team. You will implement simulation testbenches, low power simulation setup, assembly/C language diagnostics, assertion checkers or coverage monitors to meet target verification goals. You will also assist with developing test-plans, debugging failures and analyzing coverage information. Must have excellent knowledge of computer architecture and design verification fundamentals Must have experience with Verilog and popular EDA simulation, System...

We are actively hiring multiple Design Verification (DV) Engineers for Bangalore (hybrid model). If youre looking for a new challenge and can join quickly, youll be among our top-priority candidates! Open Positions : 1. DV Engineer GLS / UVM / SystemVerilog / CDC Experience : 3–8 years Skills : Gate-Level Simulations, UVM testbench development, CDC verification, timing-aware verification 2. DV Engineer – PCIe / DDR / UVM / SV Experience : 4–18 years Skills : Protocol-level verification, PCIe or DDR, UVM, SystemVerilog 3. DV Engineer – UVM / SystemVerilog Experience : 5–10 years Skills : Testbench architecture, functional verification, scalable UVM environments

Development of Specifications, Micro Architecture, RTL Development for Digital IPs. Setup and use standard EDA tools for Verification, Lint CDC, Synthesis, Power Analysis tools for Verification and Ensuring PPA for IP developed. Conduct Reviews for Documentation, RTL and Verification Tests. Experience and Skills Required 5 to 15 years of experience in SoC/IP Design. Expertise in Writing Detailed IP Specifications, Micro Architecture, IP design, Subsystem and SoC level integration. Expertise on RTL Development. Follow Coding Standards, expertise on Lint, CDC tools, verification and debugging of test cases, code and functional coverage analysis. In-depth knowledge of Clocking Methodology, Low ...

Job Description : We are looking for experienced DV Engineers with a strong background in ARM-based SoC and Subsystem Verification to join our team for exciting semiconductor projects. Key Responsibilities : Perform Design Verification of ARM-based SoC / SS level components Work on Cortex-A / Cortex-M series SoC Debug using CoreSight infrastructure (implementation or validation) Handle RTL / GLS regressions and perform deep simulation-level debugging Develop or maintain testbenches, checkers, and scoreboards in SystemVerilog/UVM Implement C/C++ modeling as needed for verification environments Technical Skills Required : Strong hands-on in SystemVerilog, UVM Experience with ARM protocols : AX...

IP/SOC Verification ,Design & Verification Failure Debugging Skills Verilog, System Verilog, & UVM Functional Coverage Development, & Coverage Closure PCIe, Ethernet, CXL, USB, CAN, LIN, FlexRay, AXI, AHB, APB Concepts in Digital Design

Description We are seeking a skilled Verification Engineer to join our team in India. The ideal candidate will have a strong background in digital design verification and will be responsible for ensuring the quality and reliability of our products through rigorous testing and analysis. Responsibilities Develop and implement verification plans and test cases for digital designs. Perform functional and performance verification using simulation and formal verification techniques. Collaborate with design engineers to understand specifications and requirements. Debug and analyze issues found during verification, providing feedback to design teams. Generate reports and documentation for verificati...

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: DV Engineer -GLS Location: Bangalore Work Type: Onsite Job Type: Full time Job Description: Key Responsibilities: Develop and implement scalable UVM-based verification environments Lead and execute GLS (Gate-Level Simulation)timing-aware and glitch-sensitive validation is a core part of this role Perform Clock Domain Crossing (CDC) verification using industry-standard methodologies Collaborate cross-functionally with RTL, DFT, and system teams for end-to-end verification closure Analyze waveforms, root-cause issues, and contribute to debugging complex logic Requirem...

Hands-on experience in IP-level Design Verification using SystemVerilog and UVM. Strong in testbench architecture, assertions, coverage, and protocol checks. Good debugging skills and experience with regressions, simulations, and functional coverage. Required Candidate profile Strong hands-on in SV/UVM, IP-level testbench, coverage, assertions, and protocol verification. Proficient in debug, simulation tools, and regression handling. Self-driven, detail-oriented

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: Design Verification Engineer Location: Bangalore Work Type: Hybrid Job Type: Full time Job Description: Over 5 years of experience in Design verification. Good exposure to Subsystem and SOC level verification. UVM, System Verilog and C based verification environment. CDC and GLS exposure DFX and DFT verification experience Exposure to Complex SOCs. Experience in High-speed protocols like PCIe, Ethernet is add on. TekWissen Group is an equal opportunity employer supporting workforce diversity.

Role & responsibilities Test bench development and debug UVM/C based test case development and debug. Power aware test case development and debug External/Internal VIP based test development and debug. Mixed-signal block modelling and RNM based testing. Coverage analysis (code, functional, assertion) Verification plan reviews, Verification reviews Back-annotated netlist simulation execution and debug Debug failing cases & Coverage improvements.

High end products (GNSS/LN 150 / MDTS / GLS/GTL /IPS 3 etc.) Responsible to achieve annual sales target & collection target. Should be having sales knowledge in High end products viz GNSS / Scanners / MDTS / Mobile mapping / Layout Navigator etc. Required Candidate profile Priorities to create direct sales network in their territory keeping focus on High end products and submitting periodical reports by adding new customers. Responsible for preparation of MIS report

Mirafra Technologies is looking for experienced Design Verification Engineers to join our dynamic team in Hyderabad/Bangalore If you're passionate about digital design and verification and want to work on cutting-edge SoC projects, this is the opportunity for you! Key Responsibilities: Develop and execute test plans and testbenches using SystemVerilog/UVM Perform functional and code coverage analysis Debug RTL and testbench issues efficiently Collaborate with design and architecture teams to ensure verification completeness Required Skills: Strong coding skills in Verilog Hands-on experience with SystemVerilog and UVM-based verification Experience in SoC/IP level verification Good understand...

Roles and Responsibilities Design verification using UVM (Universal Verification Methodology) for IP/SoC level verification. Develop test benches from scratch, including creating drivers, monitors, and predictors. Utilize System Verilog to write verification code and debug issues. Collaborate with cross-functional teams to identify requirements and develop test plans. Participate in peer reviews to ensure high-quality deliverables. Desired Candidate Profile 4-10 years of experience in SOC/IP Verification with expertise in DV on Cpu, DDR, Ethernet, PCIe protocols. Bachelor's degree (B.Tech/B.E.). Master's degree preferred but not mandatory (M.Tech). Strong understanding of GLS (Global Logic S...

Roles and Responsibilities Design verification using UVM (Universal Verification Methodology) for PCIe, DDR, Ethernet interfaces on SOCs. Develop test benches in System Verilog for verifying complex digital designs. Collaborate with cross-functional teams to identify requirements and develop test plans. Utilize GLS (Golden Labs Simulation) tools for simulation setup and debugging. Participate in peer reviews to ensure high-quality deliverables. Must have good debugging skills. Experience in any of the slow speed peripherals like I2C, SPI, UART is a plus. Desired Candidate Profile 5 years of experience in SV/UVM Lead role with expertise in design verification using UVM methodology. Bachelor's...

Job Specs : We are seeking a highly skilled and motivated ASIC SOC & GLS Verification Engineer to join the offshore development teams of our group companies. You will work with the rapidly expanding team which focuses on the research and development of ASIC Verification IPs for Silicon Lifecycle Management, driving innovation and excellence in chip design and verification. You will work alongside a talented and dedicated group of engineers, all committed to pushing the boundaries of technology and delivering top-notch solutions to our customers. Work Location : Remote, Work From Anywhere Work Expertise: 7 Years 10 Years Desired Profile : B.E./B.Tech or M.E./M.Tech in Electronics, Electrical,...

Job Summary: We are seeking a highly skilled and motivated Senior Design Verification Engineer to join our growing team. You will be responsible for planning and executing the verification strategy for complex ASIC/SoC designs. You will work closely with design, architecture, and software teams to ensure functional correctness of RTL through rigorous verification methodologies. Key Responsibilities: Develop and execute comprehensive test plans based on design specifications and architectural documents. Build and maintain constrained-random verification environments using SystemVerilog UVM . Write testbenches, test cases , and functional coverage to ensure design quality. Debug RTL and testbe...

Responsibilities: * Collaborate with cross-functional teams on ARM processor integration. * Design, verify & debug VLSI systems using SV, UVM & GLS. * Implement IP/Sub-System/SOC architecture with APB, AXI & AHB protocols. Health insurance Provident fund

We are looking for Senior SOC Verification Engineers for Hyderabad & Bangalore location. 1) SOC Verification 2) SV UVM 4) C & Verilog Language Interested candidates, Kindly share with me your updated profile to anand.arumugam@modernchipsolutions.com

Educational requirement Bachelor or Masters in EE/ECE/CS or related specializations with 3+ years of relevant experience.Strong in UVM/System Verilog/C/C++/scripting, Simulation, Formal verification. Good understanding of SoC architectures Required Candidate profile GLS verification experience at Core level. SV - UVM understanding. Scripting in perl, python. Debug of complicated designs using Verdi. Power aware verification, SDF / timing simulation.

Overview Lead Verification engineer Responsibilities As a Senior Design Verification Engineer, you will define verification methodology and implement the corresponding verification plan for the SoC. You will participate in the design verification and bring-up of the SoC by writing relevant tests, coverages, assertions, developing automation infrastructure, debugging code, test benches, test harnesses, while interacting with the extended team. You will work closely with multi-disciplinary groups including Product Design, Audio Technology, Computer Vision, Hardware and Software Engineering, to create a multi-model SoC that enables development of world-class hardware devices. Bachelor’s/ Master...

Overview UVM Based verificaton at SOC level Responsibilities As a Senior Design Verification Engineer, you will define verification methodology and implement the corresponding verification plan for the SoC. You will participate in the design verification and bring-up of the SoC by writing relevant tests, coverages, assertions, developing automation infrastructure, debugging code, test benches, test harnesses, while interacting with the extended team. You will work closely with multi-disciplinary groups including Product Design, Audio Technology, Computer Vision, Hardware and Software Engineering, to create a multi-model SoC that enables development of world-class hardware devices. Bachelor’s...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Strong knowledge of digital design and SOC architecture. Good understanding of OOP concepts Experience in HVL such as System Verilog, UVM/OVM & System C Experience in HDL such as Verilog Knowledge of ARM/DSP CPU architecture, High Speed Peripherals like USB2/3, PCIE or Audio/Multimedia Familiarity with Power-aware Verification, GLS, Test vector generation is a plus Exposure to Version managers like Clearcase/perforce Scripting language like Perl, Tcl or Python Analytical and Debugging skil Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or rel...