153 Gls Jobs - Page 2

Overview Lead Verification engineer Responsibilities As a Senior Design Verification Engineer, you will define verification methodology and implement the corresponding verification plan for the SoC. You will participate in the design verification and bring-up of the SoC by writing relevant tests, coverages, assertions, developing automation infrastructure, debugging code, test benches, test harnesses, while interacting with the extended team. You will work closely with multi-disciplinary groups including Product Design, Audio Technology, Computer Vision, Hardware and Software Engineering, to create a multi-model SoC that enables development of world-class hardware devices. Requirements Bache...

Overview UVM Based verificaton at SOC level Responsibilities As a Senior Design Verification Engineer, you will define verification methodology and implement the corresponding verification plan for the SoC. You will participate in the design verification and bring-up of the SoC by writing relevant tests, coverages, assertions, developing automation infrastructure, debugging code, test benches, test harnesses, while interacting with the extended team. You will work closely with multi-disciplinary groups including Product Design, Audio Technology, Computer Vision, Hardware and Software Engineering, to create a multi-model SoC that enables development of world-class hardware devices. Requiremen...

As a Lead Verification Engineer, you will be responsible for defining verification methodology and implementing the corresponding verification plan for the SoC. This will involve participating in the design verification and bring-up of the SoC by writing relevant tests, coverages, assertions, developing automation infrastructure, debugging code, test benches, test harnesses, while collaborating with the extended team. Your role will require close collaboration with various groups including Product Design, Audio Technology, Computer Vision, Hardware and Software Engineering, to develop a multi-model SoC that facilitates the creation of top-notch hardware devices. **Key Responsibilities:** - D...

General Summary: QCT's Bangalore Wireless R&D(WRD) HW team in Bangalore is looking for experienced Wireless HW design verification engineers to work on Qualcomms best in class chipsets for mobile phones, wearables and IOT . Candidate will be working with ASIC designs on the latest technology nodes. This role will require the candidate to understand and work on all aspects of VLSI Verification cycle like Testbench architecture, Verification Planning, Testbench and Test development, Verification closure with best-in-class methodologies. In this role of WRD Verification Engineer, you will be verifying Wifi and/or Modem from both TX and RX perspective. The responsibilities will majorly include :...

If you are passionate about pushing the boundaries of Design technology and thrive in a collaborative, dynamic environment, we invite you to join our team as a Design Engineer Join us to be part of our journey in shaping the future of SoC design and innovation, Responsibilities As a creative design engineer with a knowledge of subsystems and SoCs you will be part of a team integrating IP and developing logic for SoCs, You will work with the project team to understand and review the architecture and develop the design specifications, Your key responsibilities will include writing micro-architecture specifications, developing the RTL, fixing bugs and running various design checks, You will wor...

Role Overview: As a DV Lead Engineer at TekWissen in Mysore, your responsibilities will include: Key Responsibilities: - Build test plan, tests, coverage assertions from Specification. - Architect and build testbench and testbench components with expertise in UVM, SV, and C SVA. - Demonstrate familiarity with industry protocols like AXI, APB, AHB, PCIe, SoC. - Showcase strong debugging skills and experience with industry standard EDA tools such as Synopsys, Cadence simulators, and debugging tools. Qualifications Required: - Experience with scripting and automation. - Demonstrated leadership and collaboration abilities, including mentoring, cross-functional communication, UPF-simulations, GLS...

Job Description: Were looking for a talented GLS (Gate-Level Simulation) Verification Engineer with strong experience in verifying complex SoCs using industry-standard tools and methodologies. Key Responsibilities & Skills: * Hands-on experience in GLS verification using Cadence Xcelium (mandatory) and Synopsys VCS. * Minimum 3 years of GLS experience with a solid understanding of gate-level verification flows. * Good understanding of physical design concepts relevant to GLS verification. * Strong knowledge of SystemVerilog and UVM-based testbench environments. * Experience with DDR or HBM PHY GLS will be an added advantage. * Basic understanding of SoC design and common bus protocols (AMBA,...

Job Description: Were looking for passionate Design Verification Engineers experienced in ASIC/SoC environments to contribute to high-performance PCIe, Networking, and IP Sub-System verification using industry-leading tools and methodologies. Key Responsibilities & Skills: Develop UVM-based testbenches and verification infrastructure for complex SoC and IP subsystems. Define and execute verification plans, coverage metrics, assertions, and regression strategies. Work on block-level and subsystem-level verification, ensuring reusable and scalable verification components. Collaborate with design, validation, and integration teams to ensure end-to-end functional quality. Strong knowledge of Sys...

Job Description The Systems Development team in Arm Solutions Engineering (SE) develops compute subsystem (CSS) products and SoC's for a wide range of market segments including Client, Infra, IoT and Automotive. As part of this work, we use the latest IP products from Arm and selected 3rd party vendors. The team includes members in multiple sites including India (Bangalore), the UK (Manchester, Sheffield, Cambridge), France (Sophia), US (Austin, Chandler and San Diego) and Hungary (Budapest)! Responsibilities As a member of the Front End CAD team, you will be responsible for the development, standardization and maintenance of engineering flows that enable system verification activities withi...

Key Responsibilities Own and execute hierarchical scan insertion and ATPG flows for SoCs/MCUs Integrate and verify MBIST at RTL level across various memory instances Enable LBIST integration, RTL and gate-level coverage analysis, and GLS (Gate-Level Simulation) Implement and verify IEEE1149.1 (JTAG) and IJTAG standards for boundary scan and internal test Conduct post-silicon debug of DFT patterns and drive root-cause analysis Collaborate daily with RTL design, physical design, and verification teams to meet quality and schedule goals Support testability reviews and sign-off processes across design milestones Mentor and provide technical leadership to junior engineers in the DFT domain

As a Finance & Accounting Manager at Swish Club, you will play a crucial role in overseeing all accounting operations to ensure compliance and accuracy in financial reporting. Your expertise in accounting and financial management will be instrumental in driving the company's success. Here's what you can expect in this role: You will be responsible for closing the book of accounts periodically, preparing reconciliation statements, and reviewing and presenting MIS reports. Your understanding of reporting requirements, GLs, and processes will be crucial in maintaining accuracy and completeness in accounting processes. Additionally, you will ensure statutory and regulatory compliances and manage...

You will be joining Simpolo Tiles and Bathware as a Senior Executive - Finance, based in Ahmedabad. Your primary responsibilities will include: - Overseeing day-to-day operations and reviews of GL's - Managing the functioning of the F&A team and external agencies - Assisting in timely and accurate monthly/yearly book closure and MIS reporting - Ensuring compliance with auditing standards & IND AS - Preparing financial statements as per IND AS for Indian and foreign subsidiaries - Monitoring, leading, and evaluating internal controls and financial controls - Coordinating and concluding statutory audits - Having a strong understanding of IND AS, CARO reporting, auditing standards, SEBI LODR, I...

Design Verification Experience : 3-5 years Location : Bangalore Following skill set is required: Candidate must have GLS hands on experience in ZD/PAGLS/SDF/Scan dump verification. Strong Debug, UVM, System Verilog and Digital Fundamentals Should be able to debug Netlist functional failure. Low Power Awar verification. Timing Simulation failure, setup and hold violation fundamentals. Scan dump verification. Understanding Specs and Standards and developing relevant test plans. Monitors, scoreboards, sequencers and sequences, that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved. Good understanding of DDR families (LP/PC) and g...

As a VLSI Engineer at Qualcomm India Private Limited, you will have the opportunity to work with cross-functional engineering teams in all stages of the design and development cycles. Your responsibilities will include: - Demonstrating strong knowledge of digital design and SOC architecture - Having a good understanding of OOP concepts and experience in HVL such as System Verilog, UVM/OVM & System C - Utilizing experience in HDL such as Verilog - Possessing knowledge of ARM/DSP CPU architecture, High-Speed Peripherals like USB2/3, PCIE, or Audio/Multimedia - Being familiar with Power-aware Verification, GLS, Test vector generation (a plus) - Having exposure to Version managers like Clearcase...

Job Title: VLSI Verification Engineer Experience: 1 to 3 years Location: Hyderabad Job Description: We are seeking a highly motivated VLSI Verification Engineer with hands-on experience in circuit simulation, gate-level verification, and schematic analysis . The candidate will work on SPICE-based simulations, GLS with SDF back annotation, and transistor-level debugging to ensure design quality and sign-off readiness. Key Responsibilities: Develop, understand, and analyze block-level & memory schematics. Perform SPICE simulations (DC, transient) and correlate with gate-level models. Conduct gate-level simulations with SDF back annotation. Debug annotation issues, timing violations, and GLS fa...

Role Overview: You will be responsible for implementing Design for Test (DFT) techniques to ensure the quality and reliability of semiconductor products. Your primary focus will be on areas such as JTAG, ATPG, logic diagnosis, Scan compression, and MBIST/LBIST. Additionally, you will be involved in Tessent based ATPG flow, GLS, and Post-silicon-debug. Your expertise in Perl/Tcl/Python scripting will be crucial for this role. Key Responsibilities: - Utilize your strong fundamental knowledge of DFT techniques to perform Core and SOC level ATPG, ensuring Automotive grade quality. - Engage in hierarchical ATPG retargeting and Pattern release for application on ATE. - Conduct SOC and Core level T...

order General information #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in? We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness,...

JD : Verification of Debug Subsystem Requirement: 6 years exp Job Profile & Expertise Requirements: End to end Debug Subsystem verification Expertise in RTL DV, GLS, Coverage closure Understanding of ARM Coresight Debug Architecture Work with architecture and SW teams for debug system requirements, Define VPlan ARM-based CPU debug system understanding - trace, crash debug CPU knowledge and expertise in C Strong SV, UVM knowledge

1. RTL development and Verification for Digital subsystems, Memory Subsystems including BIST. 2. DFT Insertion and Verification signoff for IO, ARM-PNR, Memory Digital Subsystems with Tessent/Embedded MBIST 3. MBIST, ATPG, RSQ Verification and sign-off. 4. Formal verification, Cross Clock Domain checks, Power/Timing sign off 5. Verify complex Digital subsystems through OVM, UVM methodology, creating the Verification Suit Independently. Skillset: 1. Hands on Experience with RTL, Synthesis, 2. Hands on experience in defining ICC/Synthesis constraints that meets timing closure needs 3. Familiarity with DFT flows includes MBIST, ATPG, RSQ and Verification methodologies and best practices for the...

What You''ll Do Cisco SiliconOne team is looking for an expert and talented ASIC Engineer. You will have an ASIC design background with hands-on experience in RTL design with in-depth knowledge of ASIC/SoC development cycle, the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume products. Responsibilities Looking for a Front-end Design ASIC Engineer. Architectural work: in-depth understanding of the architecture, and identification of problems and solutions. All aspects of implementation: specification, design, timing-analysis, power-optimization, flow automation, optimization of the logic for ...

You will be working as a DV Engineer at Qualcomm India Private Limited with a focus on SOC design verification. Your main responsibility will be to understand the internal requirements and complexities of highly complex auto, compute, mobile, XR-VR, IoT SOCs and architect the required verification strategy. You will help set up methodologies, develop test plans, and verify that the design meets the highest quality standards. Your early involvement in DV will also require you to participate in architecture/product definition through early involvement in the product life-cycle. **Key Responsibilities:** - Define verification architecture, develop test plans and build verification environment -...

Demonstrate a solid understanding of the CPU/CPU Based SoC Verification. Must have good understanding of one or more of the following domains ARM v8/v9, RISC-V, x86 Architecture Memory Architecture(DRAM, Cache, MMU), GIC, SoC Debug Architecture Cache Coherent Architectures PCIe OSCI Layer and its functionality PCIe Phy , Bring up and trainin SoC DV, BUS Interconnects Understand architecture and micro-architecture specifications. Work closely with Architects and Logic Designers. Develop Unit Level and/or Subsystem Level Test plans, Coverage Plans and checker Plans needed to target zero defect post-silicon quality. Develop scalable Test benches in System Verilog and UVM. Develop Tests, Functio...

Demonstrate a solid understanding of the CPU/CPU Based SoC Verification. Must have good understanding of one or more of the following domains ARM v8/v9, RISC-V, x86 Architecture Memory Architecture(DRAM, Cache, MMU), GIC, SoC Debug Architecture Cache Coherent Architectures PCIe OSCI Layer and its functionality PCIe Phy , Bring up and trainin SoC DV, BUS Interconnects Understand architecture and micro-architecture specifications. Work closely with Architects and Logic Designers. Develop Unit Level and/or Subsystem Level Test plans, Coverage Plans and checker Plans needed to target zero defect post-silicon quality. Develop scalable Test benches in System Verilog and UVM. Develop Tests, Functio...

We are looking for a skilled Observability Engineer with 4 to 7 years of experience. The ideal candidate will have expertise in Data Integration & Standardization, OTEL, Java, Python, or frontend languages, and Grafana. This position is available in Bangalore, Mumbai, Chennai, Hyderabad, Noida, and Gurgaon. Roles and Responsibility Design and implement data integration solutions using various tools and technologies. Develop and manage data aggregation techniques to ensure data quality and integrity. Collaborate with cross-functional teams to identify and prioritize project requirements. Implement and manage data ingestion pipelines to support business intelligence initiatives. Troubleshoot a...

Job Description: We're looking for a verification SME, responsible for the SoC verification process and designing the next-generation HBM DRAM products. Deep understanding of SoC Verification, testbench architecture, SoC verification methodologies, and 2.5D & 3D package integration. Responsibilities: • Develop test plans at SOC Level and analyze Coverage. • Build verification environments to verify complex SOCs. • Develop Random/Directed test in RTL and GLS environments. • Review architectural specifications to ensure high quality. • Work with customers to understand their verification &validation requirements • Debug and identify root causes and solutions for pre-silicon and post-silicon is...