6 Fv Jobs

As a Key Account Manager based in Gurgaon with 4+ years of experience, your primary responsibilities will include dealing with Store Managers and Floor executives. You should possess good knowledge of A+ Stores in Pune and be adept at opening new B2B Clients while managing existing relationships. Utilizing reporting software effectively and ensuring collection from the market within agreed terms will be crucial aspects of the role, with a primary focus on maintaining profit margins as the main KRA. Your preferred area of operations will be Pune, and you should have a strong understanding of the horeca segment while handling ecommerce business operations. Collaboration with the Operations team to obtain daily forecasts and working on SKU wise sales plans will be essential to determine where and what to sell. Ideal candidates for this position will hold a Graduation or MBA degree, with additional preference given to those with knowledge of organic, regenerative, or pesticide-free farming. Strong communication skills in English, Hindi, and the local language are required, along with proficiency in MS Office. A background in Modern Trade Sales, particularly in the F&V sector, is preferred. Possession of a valid 2W/4W driving license and access to your own 2W/4W vehicle is also necessary. If you meet the qualifications and possess the skills mentioned above, we encourage you to apply for this exciting opportunity as a Key Account Manager.,

Qualcomm India Private Limited is looking for an experienced ASIC Design Engineer to join their Engineering Group, Hardware Engineering division. As an ideal candidate, you should hold an MTech/BTech in EE/CS with a minimum of 7 years of experience in ASIC design. Your responsibilities will include micro-architecture development, RTL design, front-end flows, synthesis, DFT, FV, and STA. A good understanding of DDR families and generations, as well as protocols like AHB/AXI/ACE/CHI, will be advantageous. Experience with post-silicon bring-up and debug is a plus. You should be able to collaborate effectively with global teams and possess strong communication skills. Hands-on experience in Multi Clock designs, Asynchronous interface, and Low power SoC design is essential for this role. Your key responsibilities will involve micro-architecture & RTL development, validation for linting, clock-domain crossing, and DFT rules. You will work closely with the functional verification team on test-plan development and waveform debugs at various levels. Experience in constraint development, timing closure, UPF writing, power aware equivalence checks, and low power checks is required. Additionally, you will be supporting performance debugs and addressing performance bottlenecks, along with providing assistance in sub-system, SoC integration, and chip-level debug. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please contact disability-accommodations@qualcomm.com. Qualcomm expects all employees to adhere to applicable policies and procedures, including those related to the protection of confidential information. If you meet the following qualifications and have the required experience, we encourage you to apply for this exciting opportunity at Qualcomm India Private Limited.,

Qualcomm India Private Limited is seeking a candidate with a minimum of 4 to 8 years of work experience in ASIC RTL Design, Synthesis, STA & FV. The ideal candidate should have experience in Logic design/micro-architecture/RTL coding, along with hands-on experience in designing and integrating complex multi clock domain blocks. Proficiency in Verilog/System-Verilog and knowledge of AMBA protocols like AXI, AHB, APB, clocking/reset/debug architecture are necessary. Experience in Multi Clock designs and Asynchronous interface is a must, as well as familiarity with tools in ASIC development such as Lint, CDC, Design compiler, and Primetime. Collaboration with Design verification and validation teams for pre/post Silicon debug is expected, and hands-on experience in Low power design is preferable. Additionally, experience in Synthesis and understanding of timing concepts for ASIC is essential. The minimum qualifications for this position include a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 3+ years of Hardware Engineering or related work experience. Alternatively, a Master's degree in the relevant fields with 2+ years of experience or a PhD with 1+ year of experience would also be considered. Qualcomm is an equal opportunity employer committed to providing accessibility to individuals with disabilities throughout the application/hiring process. Reasonable accommodations can be requested by emailing disability-accommodations@qualcomm.com or calling Qualcomm's toll-free number. Employees are expected to adhere to all applicable policies and procedures, including security and confidentiality requirements. Qualcomm's Careers Site is exclusively for individuals seeking job opportunities at Qualcomm. Staffing and recruiting agencies are not authorized to use the site or submit profiles, applications, or resumes on behalf of individuals. Unsolicited submissions from agencies will not be accepted, and Qualcomm does not bear responsibility for any fees related to such submissions. For more information about this role, please contact Qualcomm Careers.,

As a Qualcomm Hardware Engineer, you will play a crucial role in the planning, design, optimization, verification, and testing of electronic systems. Your responsibilities will include working on various types of systems such as circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment, packaging, test systems, FPGA, and/or DSP systems to help in the development of cutting-edge products. You will be involved in the front-end implementation of MSIP designs, RTL development, validation for linting, clock-domain crossing, low power and DFT rules, and collaborating with the functional verification team on test-plan development and debug. Your role will also entail developing timing constraints, providing support for physical design team, UPF writing, power-aware equivalence checks, low power checks, DFT insertion, ATPG analysis, SoC integration support, and chip level pre/post-silicon debug. To be successful in this role, you should hold an MTech/BTech in EE/CS with at least 5 years of hardware engineering experience. You should have expertise in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks), synthesis, DFT, functional verification, and static timing analysis. Experience with post-silicon bring-up and debug will be an added advantage. Additionally, the ability to collaborate effectively with global teams and strong communication skills are essential for this role.,

As an ideal candidate for this role in Bengaluru, you should possess a solid understanding of Synthesis, Static Timing Analysis (STA), and Formal Verification (FV) concepts. Additionally, expertise in Place and Route (PNR) along with STA knowledge would be advantageous. With 3 to 5 years of experience, you will play a key role in leveraging your skills to contribute effectively to the team.,

As a Hardware Engineer at Qualcomm, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems including circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to develop cutting-edge products. Collaboration with cross-functional teams is essential to meet performance requirements and deliver innovative solutions. To qualify for this role, you must hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with a minimum of 4 years of Hardware Engineering experience. Alternatively, a Master's degree with 3+ years of experience, or a PhD with 2+ years of experience can also be considered. Additionally, candidates with a Bachelor's degree and 2+ years of experience, a Master's degree and 1+ year of experience, or a PhD with relevant experience are eligible. The ideal candidate should possess good hands-on experience in Floorplanning, PNR, and STA flows, as well as knowledge of Placement/Clock Tree Synthesis (CTS) and optimization. Familiarity with signoff domains such as LEC, CLP, and PDN is required, along with proficiency in Unix/Linux, Perl, TCL scripting. Key responsibilities include taking ownership of PNR implementation on the latest nodes, covering tasks like Floorplanning, Placement, CTS, and post-route activities. Signoff knowledge is crucial, encompassing areas like STA, Power analysis, FV, low power verification, and PV. A quick learner with strong analytical and problem-solving skills will excel in this role. Qualifications for this position include a minimum of 15 years of Hardware Engineering experience or related work experience, along with expertise in PNR flow for advanced tech nodes like 4nm, 5nm, 7nm, and beyond.,