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Senior Design Verification Engineer BITSILICA

0.0 years

0 Lacs

hyderabad, telangana, india

On-site

Verification Test bench development and debug UVM/C based test case development and debug. Power aware test case development and debug External/Internal VIP based test development and debug. Mixed-signal block modelling and RNM based testing. Coverage analysis (code, functional, assertion) Verification plan reviews, Verification reviews Back-annotated netlist simulation execution and debug Debug failing cases & Coverage improvements.

Posted 5 days ago

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