5.0 - 10.0 years

0 Lacs

pune, maharashtra

On-site

ACL Digital is searching for a skilled and experienced Static Timing Analysis (STA) Engineer to become a part of the growing VLSI team. If you possess expertise in timing analysis and have previously handled full-chip designs, we are interested in hearing from you. As an STA Engineer at ACL Digital, your responsibilities will include driving full-chip STA from RTL to GDSII, developing and verifying timing constraints (SDC) for intricate SoCs, conducting timing closure and sign-off utilizing tools such as PrimeTime, collaborating with RTL, physical design, and DFT teams for ECOs and timing fixes, as well as analyzing timing reports, debugging violations, and suggesting optimization strategies. The ideal candidate should have 5-10 years of hands-on experience in Static Timing Analysis, a proven track record in full-chip STA and timing sign-off, a strong understanding of timing constraints, multi-mode/multi-corner (MMMC) flows, familiarity with scripting languages (TCL, Perl) and STA tools (preferably Synopsys PrimeTime), and excellent analytical, debugging, and cross-team communication skills. This position is based in Pune/Bangalore and requires an immediate notice period. Join ACL Digital to be a part of a dynamic team delivering next-gen semiconductor solutions. You will have the opportunity to work on cutting-edge technology projects with top-tier clients globally.,

Posted 2 weeks ago

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