Senior Front End Integration - STA Engineer Advanced Micro Devices (AMD)

5.0 - 10.0 years

5 - 10 Lacs

Hyderabad, Telangana, India

On-site

KEY RESPONSIBILITIES: Front-end implementation from RTL to netlist, including RTL Lint, CDC/RDC analysis, timing constraints, Power Analysis, STA for Multi-Media IPs Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power. Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failures Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them. Analyze the inter-block timing and come up with IO budgets for the various partition blocks. Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC. Perform RTL Lint and work with the Designers. Analyze RTL CDC/RDC and work with Designer for potential Clock and Reset Design Domain crossing issues. Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults. Perform Power Estimation at RTL and Gate Level and identify power reduction opportunities. Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA, Power). Implementing Functional ECOs using Conformal and writing manual Ecos. Work with Architects, RTL Designers and SOC teams for efficient IP Quality. PREFERRED EXPERIENCE: 5 to 10 years of experience inFront-end implementation from RTL to netlist Familiarity withPower Analysis Experience/Background on Computing/Graphics is a benefit ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

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