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4.0 - 8.0 years
0 Lacs
karnataka
On-site
As a member of our team, you will have the opportunity to work on cutting-edge Application-specific integrated circuit (ASIC) projects that are at the forefront of technology. Your role will involve collaborating with various teams within the organization, such as architecture, verification, power and performance, and physical design, to develop high-quality designs for next-generation data center accelerators. You will be responsible for defining and implementing physical design methodologies, taking ownership of specific design partitions or top-level designs, and ensuring the closure of timing and power consumption aspects of the design. Your contributions to design methodology, libraries, and code reviews will be crucial in delivering successful projects. In this role, you will also play a key part in defining physical design-related rule sets for functional design engineers. Your expertise in advanced design principles, including clock/voltage domain crossing, Design for Testing (DFT), and low power designs, will be essential in shaping the future of our hardware experiences. We are looking for individuals with a Bachelor's degree in Electrical Engineering or equivalent practical experience, along with at least 4 years of experience in advanced design. A Master's degree in Electrical Engineering or a related field is preferred. Experience with System Verilog, scripting with TCL, and VLSI design in SoC will be advantageous for this role. Join us in developing custom silicon solutions that drive innovation and power Google's direct-to-consumer products. Your contributions will play a vital role in delivering unparalleled performance, efficiency, and integration, shaping the next generation of hardware experiences loved by millions worldwide.,
Posted 1 week ago
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