9 Fpga Verification Jobs

Hi, Greetings from Thales India Pvt Ltd.....! We are hiring for Senior Engineer/Technical Lead - FPGA Verification for our Engineering competency center for Bangalore Richmond Road location. FPGA Verification Thales India Engineering Competency Center (ECC) in Bangalore is seeking a FPGA professional to be part of Hardware engineering team. In this role, you will be responsible for Hardware subsystems architectural design, trade-off analysis, feasibility studies, Proposal preparation, detailed design and IVVQ for various Thales products (Defense and aerospace applications) including Obsolescence redesign. Qualifications : B. Tech in Electronics, Instrumentation engineering or equivalent with...

Job Description Job Description Overview As a leading global aerospace company, Boeing develops, manufactures, and services commercial airplanes, defense products and space systems for customers in more than 150 countries. As a top U.S. exporter, the company leverages the talents of a global supplier base to advance economic opportunity, sustainability, and community impact. Boeing's team is committed to innovating for the future, leading with sustainability, and cultivating a culture based on the company's core values of safety, quality, and integrity. Technology for today and tomorrow The Boeing India Engineering & Technology Center (BIETC) is a 5500+ engineering workforce that contributes...

Role Overview: You will be part of the Hardware Platform Group, specializing in FPGA verification. Your responsibilities will include crafting the DV architecture, test plan, coverage plan, and ensuring bug-free RTL for first-pass success on the board. Collaboration with remote teams based in the US and Italy will be a key part of your role. Key Responsibilities: - Lead and mentor a team of verification engineers to develop robust test benches, coverage plans, and constrained random tests. - Ensure high-quality FPGA/ASIC designs through sophisticated verification techniques and comprehensive debugging. - Contribute to the adoption and evolution of verification methodologies like UVM/VMM to i...

Role Overview: You will be responsible for RTL verification and developing SV/UVM testbenches at Top/Sub-system/Block-levels. Your role will involve driving test plan and test spec development, executing tests, and generating relevant documents. Additionally, you will contribute to verification environment architecture and methodology development. The position requires experience in System Verilog, UVM programming, and verification of protocols like Ethernet, PCIe, SPI, I2C, and USB. Strong debugging skills, familiarity with Xilinx technology, FPGA verification, and scripting languages like Perl, Python, or TCL are also essential for this role. Key Responsibilities: - Develop SV/UVM testbenc...

Boeing India Engineering has an immediate opening for an Engineering Manager - Digital Circuits who will be responsible for development and management of engineers in India to perform engineering work-statements for Boeing product life cycle management. This position will work collaboratively with teams from across the globe in an integrated design environment to help deliver an engineering statement of work. The selected individual will develop and handle Engineers, interact with the program leaders from across the globe, with a vision to grow ownership in execution with their team. This position will be in Bengaluru, India , and will be reporting directly to the Sr. Electronic Manager, Ind...

As a part of the Hardware Platform Group specializing in FPGA verification, you will be responsible for a range of tasks related to crafting the DV architecture, test plan, and coverage plan for both data-path and control-path FPGAs. Your main objective will be to ensure bug-free RTL for first-pass success on the board by leveraging industry-standard tools for simulation, linting, coverage, and assertions. Collaboration with remote teams in SJC and Vimercate is an essential part of this role. Your impact in this position will involve leading and mentoring a team of verification engineers to develop robust test benches, coverage plans, and constrained random tests. By employing sophisticated ...

As a Lead Verification Engineer with over 7 years of experience, you will be an integral part of a geographically distributed verification team working on next-generation ASIC and FPGAs. Your responsibilities will include developing testplans, implementing testbenches, creating testcases, and ensuring functional coverage closure. Additionally, you will handle regression testing, contribute to verification infrastructure development, and develop both directed and random verification tests. In this role, you will be expected to debug test failures, identify root causes, and collaborate with RTL and firmware engineers to resolve design defects and test issues. You will also review functional an...

Job Title : C++ Developer - SNORT & Compiler Design Location : Bangalore Experience : 8 to 12 Years Employment Type : Full-Time Job Overview : We are looking for an experienced C++ Developer with deep expertise in SNORT rule sets, compiler development, and FPGA-accelerated processing. This role requires a strong foundation in system-level programming, along with the ability to work on performance-critical data path processing for network security applications. Key Responsibilities : - Design and develop a C++/C-based compiler to convert SNORT rule sets into state tables - Implement regex lookup engines integrated with FPGA-based acceleration - Optimize rule parsing, conversion logic, and dat...

Job Overview : We are looking for an experienced C++ Developer with deep expertise in SNORT rule sets, compiler development, and FPGA-accelerated processing. This role requires a strong foundation in system-level programming, along with the ability to work on performance-critical data path processing for network security applications. Key Responsibilities : - Design and develop a C++/C-based compiler to convert SNORT rule sets into state tables - Implement regex lookup engines integrated with FPGA-based acceleration - Optimize rule parsing, conversion logic, and data path evaluation pipelines - Collaborate with hardware (FPGA) teams to align on rule engine performance - Handle result process...