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RTL Design Engineer TekPillar

5.0 - 8.0 years

13 - 23 Lacs

noida, ahmedabad

Work from Office

Strong hands-on experience with Verilog and Xilinx Vivado design suite. knowledge of FPGA Architecture, Synthesis Flows, Timing closure. Must have work with Xilinx, Zynq, UltraScale+ platforms. Interfacing protocols: I2C, SPI, DDR, EMMC, AMBA, etc. Required Candidate profile Seeking a Senior RTL Design Engineer with strong Verilog and FPGA expertise to deliver high-performance digital designs on Xilinx platforms while collaborating with cross-functional teams.

Posted 2 days ago

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