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RTL Design Engineer TekPillar

5.0 - 8.0 years

15 - 25 Lacs

pune, ahmedabad, gurugram

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Designation: RTL Design Engineer Experience: 5 To 8 Years Location: Noida / Ahmedabad Key Responsibilities Design, develop, and verify FPGA modules using Verilog. Work with Vivado for synthesis, simulation, and implementation. Develop solutions on Xilinx Zynq UltraScale+ platforms. Integrate and interface peripherals such as I2C, SPI, DDR, EMMC, AMBA, PL, PS , etc. Collaborate with hardware, software, and system teams for end-to-end design delivery. Required Skills & Qualifications 5+ years of strong hands-on experience with Verilog . Bachelors or Masters degree in Electronics Engineering , Computer Engineering , or related fields. Proficiency with Xilinx Vivado design suite. Strong knowledg...

Posted 14 hours ago

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