775 Fpga Jobs - Page 3

Job Area: Engineering Group, Engineering Group > Systems Engineering General Summary: Highly skilled SystemC Modeling Engineer is required to join dynamic and innovative NoC Systems team in Qualcomm Bangalore Design Center. The ideal candidate will have a strong background in digital design and a deep understanding of SystemC for hardware modeling and simulation. This role involves developing and maintaining high-quality SystemC models for complex digital systems, collaborating with cross-functional teams, and ensuring that Qualcomm products meet the highest standards of performance and reliability. Key Responsibilities: Model Development: Design and implementation of SystemC models for digital systems, including processors, memory controllers, and peripheral interfaces. Methodology Awareness of Virtual prototypes and Performance modeling using C++/SystemC/TLM 2.0. Approximately timed and Loosely Timed(LT) style of coding for software development when using Virtual Prototype Verification: Development and executution of testbenches to verify the correctness and performance of SystemC models. Optimization: Optimization of models for simulation speed and resource efficiency. Documentation: Creation and maintenance of detailed documentation for models, testbenches, and verification plans. Collaboration: Work closely with hardware and software engineers to ensure seamless integration of SystemC models into the overall system design. Troubleshooting: Identify and resolve issues in the modeling and simulation process. Research: Stay updated with the latest advancements in SystemC and digital design techniques. Technical Skills Proficient in SystemC and C++. Strong understanding of digital design principles and techniques. Experience with hardware description languages (HDLs) such as Verilog is a plus. Familiarity with simulation tools and environments is a plus. Soft Skills Excellent problem-solving and analytical skills. Strong communication and collaboration abilities. Ability to work independently and in a team environment. Attention to detail and a commitment to quality. Preferred Skills Experience with Network-on-chip, high-performance computing and parallel processing. Knowledge of ASIC design. Familiarity with scripting languages (e.g., Python, Perl). Experience with version control systems (e.g., Git). Qualifications: Education: Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field. Experience: 5 to 10 years of experience in digital design and SystemC modeling. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Principal Design Verification Engineer Job Overview MIPS is seeking a highly experienced Senior Staff Design Verification Engineer with over 15 years of industry experience to lead verification efforts focused specifically on Coherency Manager and Cache Controller components. The successful candidate will have extensive hands-on experience utilizing advanced verification methodologies, including constrained random testing, formal verification, and coverage-driven verification. This senior role involves close collaboration with CPU architects, designers, and cross-functional global teams to ensure high-quality, high-performance processor designs. Key Responsibilities Lead and drive verification activities for Coherency Manager and Cache Controller IP to closure. Collaborate closely with design teams and architects to thoroughly understand and interpret microarchitectural and functional specifications. Develop comprehensive verification plans and execute these plans through testbench creation, test case development, and rigorous analysis. Create directed and constrained random test cases in SystemVerilog, Assembly, and C to verify complex coherency and cache management behaviors. Employ formal verification techniques to augment random verification and ensure exhaustive coverage. Analyze verification coverage metrics to identify and close coverage gaps efficiently. Automate and optimize verification flows and regression environments using scripting languages like Python, Perl, TCL, or Shell. Mentor junior verification engineers, providing technical guidance and leadership within the verification team. Qualifications Master`s degree or higher in Electronics, Electrical, Computer Engineering. 15+ years of relevant verification experience, specifically in CPU or complex SoC verification. Proven expertise in verification of Multicore and Multicluster Coherency, Cache Controllers, or similar blocks. Deep knowledge and practical experience with verification methodologies such as UVM, constrained random, and formal verification. Proficiency in SystemVerilog, Verilog, C, C++, and Assembly. Solid understanding of interconnect and coherency protocols such as AXI, ACE, OCP, CHI. Strong scripting skills in Python, Perl, TCL, or Shell. Experience with CPU architectures, particularly RISC-V, ARM, or MIPS. Preferred Experience Experience with RISC-V architecture. Familiarity with functional safety standards (e.g., ISO 26262). Prior exposure to FPGA prototyping and emulation platforms. What MIPS Offers Opportunity to be part of a dynamic team creating industry-leading RISC-V processors. Autonomy with extensive support from industry experts. Opportunities for significant career growth and technical advancement. Competitive compensation and comprehensive benefits package About MIPS MIPS is a pioneer in RISC-based computing with a legacy of innovation in high-performance microprocessor design. Today, MIPS continues this legacy by leading the adoption and advancement of the RISC-V architecture, delivering scalable processor solutions for cutting-edge computing applications.

• Experience in behavioural, post synthesis verification/ simulation with Xilinx FPGA tools. • Good knowledge in static timing analysis and clock domain crossing techniques. • Experience in writing Verilog/ VHDL code for peripheral interface like LCD/ LED Displays/ Keypads, serial memories over Parallel/ SPI/ UART, I2C interfaces. • Good experience in porting and validating the code on custom hardware boards. • Knowledge and experience of defining HW/ FW interfaces. • Experience in on board debugging using chipscope,ILA and data capture tools. • Experience in the following is a plus: - AMBA protocols (AXI, AHB, APB) - In hardware design involving FPGA and associated component selection, schematic preparation, PCB artwork guidance and board testing will be supplemental. - Experience in writing code for digital signal processing techniques (like FIR, CIC filters, Equalizer and MODEM) in FPGAs. - Knowledge in Matlab scripting language.

Project Role : Application Developer Project Role Description : Design, build and configure applications to meet business process and application requirements. Must have skills : PySpark Good to have skills : NAMinimum 3 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Lead, you will lead the effort to design, build, and configure applications, acting as the primary point of contact. Your typical day will involve collaborating with various stakeholders to gather requirements, overseeing the development process, and ensuring that the applications meet the specified needs. You will also be responsible for troubleshooting issues and providing guidance to team members, fostering a collaborative environment that encourages innovation and efficiency in application development. Roles & Responsibilities:- Expected to perform independently and become an SME.- Required active participation/contribution in team discussions.- Contribute in providing solutions to work related problems.- Facilitate knowledge sharing sessions to enhance team capabilities.- Mentor junior team members to support their professional growth. Professional & Technical Skills: - Good to have skills - AWS S3, DeltaLake, Airflow- Experience should be 4+ years in Python- Candidate must be a strong Hands-on senior Developer- Candidate must possess good technical / non-technical communication skills to highlight areas of concern/risks- Should have good troubleshooting skills to do RCA of prod support related issues Additional Information:- The candidate should have minimum 3 years of experience in PySpark.- This position is based at our Bengaluru office.- A 15 years full time education is required.- Candidate must be willing to work in Shift B i.e. from 11 AM IST to 9PM IST. Also, do the weekend support as per a pre-agreed rota. Compensation holiday may be provided for the weekend shift Qualification 15 years full time education

This role involves the development and application of engineering practice and knowledge in the following technologies: Electronic logic programs (FPGA, ASICs); Design layout and verification of integrated circuits (ICs), printed circuit boards (PCBs), and electronic systems; and developing and designing methods of using electrical power and electronic equipment. Focus on Electrical, Electronics Semiconductor. Entry level graduate with limited commercial and technical work experience. Build skills and expertise in a chosen Engineering Discipline. Works to instructions and directions and delivers reliable results. Keen to understand clients business needs. Solves routine problems. Organises own time with a short time horizon.,

Role : RTL Software Testing Engineer Role does not involve Silicon RTL development and neither any HW flow or testing. Work Location: Hyderabad Qualification: B.E / B. Tech or M. Tech in ECE / CS / EEE Experience Level : Minimum 2+ years Job Description Excellent Knowledge in Tcl, Python scripting. to test cases.(This would be the primary responsibility) Vivado testing of synthesis tool and other stages. RTL Coding in Verilog, System Verilog, or VHDL Strong understanding of FPGA flow, Logic design, Digital design etc. Knowledge in Xilinx FPGA architecture Communication Skills: Ability to communicate technical information in an organized and understandable fashion. Customer oriented approach with a demonstrated concern and desire to work with and assist customers. Good organizational skills with the ability to multitask, prioritize, and track many activities. Outstanding oral and written communication skills.

FPGA Engineer by Advantal Technologies | Jul 25, 2025 | Jobs | 0 comments Location: Bengaluru (Client Site) Job Type: Full-time Experience: 3-7 years Notice Period: 0-15 days (immediate joiners preferred) No. of Positions: 1 Lead & 4 Engineers About the Role: We are seeking a skilled FPGA Engineer with 3 7 years of experience in RTL design using Verilog, along with expertise in Xilinx MPSoC platforms, MicroBlaze processor development, and embedded system security aspects such as authentication, encryption/decryption, and certificates. The ideal candidate will play a key role in architecting and implementing secure, high-performance digital logic systems. Requirement: Experience band 3-7 years Experience in RTL coding using Verilog Experience on development on Xilinx MPSoC (preferably ZCU 106/104) Hands-on experience with Xilinx Vivado and Vitis Desirable to have experience with MISRA C coding guidelines Desirable to have experience with DO-254 Desirable to have experience with Microblaze Desirable to have experience in security aspects of authentication, certificates, encryption/decryption How to Apply: If you are passionate about embedded systems and meet the above requirements, we would love to hear from you. For more information, connect with us at : +91 91312 95441 Location: Bengaluru (Client Site) Job Type: Full-time Experience: 3-7 years Notice Period: 0-15 days (immediate joiners preferred) No. of Positions: 1 Lead & 4 Engineers About the Role: We are seeking a skilled FPGA Engineer with 3 7 years of experience in RTL design using Verilog, along with expertise in Xilinx MPSoC platforms, MicroBlaze processor development, and embedded system security aspects such as authentication, encryption/decryption, and certificates. The ideal candidate will play a key role in architecting and implementing secure, high-performance digital logic systems. Requirement: Experience band 3-7 years Experience in RTL coding using Verilog Experience on development on Xilinx MPSoC (preferably ZCU 106/104) Hands-on experience with Xilinx Vivado and Vitis Desirable to have experience with MISRA C coding guidelines Desirable to have experience with DO-254 Desirable to have experience with Microblaze Desirable to have experience in security aspects of authentication, certificates, encryption/decryption How to Apply: If you are passionate about embedded systems and meet the above requirements, we would love to hear from you. For more information, connect with us at : +91 91312 95441

This role involves the development and application of engineering practice and knowledge in technologies such as Electronic logic programs (FPGA, ASICs), design layout and verification of integrated circuits (ICs), printed circuit boards (PCBs), and electronic systems. You will be responsible for developing and designing methods of using electrical power and electronic equipment. Focus on Electrical, Electronics, and Semiconductor domains, you will be developing competency in your area of expertise. It is expected that you will share your expertise with others, providing guidance and support as needed. You will be interpreting clients" needs and completing your role independently or with minimum supervision. In this role, you will be identifying problems and relevant issues in straightforward situations and generating solutions. Collaboration in teamwork and effective interaction with customers will be crucial for success in this position.,

You will be a member of the FPGA development team designing and developing complex FPGAs for use in state-of-the-art embedded systems. As an FPGA Senior Design Engineer / Module Lead, you will be involved in requirements gathering, architecture and detailed design of FPGAs, coding, code walk, development of verification and validation plans, documentation of design, verification / validation, user guides, etc., technical reviews, maintaining Quality standards as per the Project Quality Guidelines and mentoring team members. Experience in architecture design, development and verification of complex FPGAs is crucial for this role. You should possess excellent RTL coding skills in Verilog/VHDL and be familiar with AMD (Xilinx) / Intel (Altera) / Lattice / Microchip FPGAs. Additionally, familiarity with AMD (Xilinx) ISE, Vivado / Intel (Altera) Quartus / Lattice Diamond / Microchip Libero FPGA tools is required. Experience in Functional verification using ModelSim and familiarity with high-speed interfaces such as PCIe, SPI-4.2, SFI-4.2, Gigabit Ethernet, UTOPIA, POS PHY, USB2/3, DDR3, SPI, UART, I2C, Aurora etc. is necessary. Exposure to FPGA Static Timing Analysis and knowledge of scripting languages like TCL and Python are desired skills. You should also have knowledge of Interfacing FPGA to ADC, DACs and experience in FPGA on-chip debugging with Chipscope/ Signaltap. Test bench development in VHDL / Verilog / System Verilog and familiarity with hardware test equipment like High-Speed DSO, Logic Analyzer, Spectrum Analyzer, Network Analyzers, Traffic Generators, etc. are important aspects of this role. Understanding of high-speed Microprocessors / Micro-controllers, L2/L3 switching, TCP/IP, and other networking protocols is beneficial. Knowledge of Hardware Schematics, Quality Process, and Configuration Management tools is also required for this position. Good oral and written communication skills, strong organizational, presentation, and motivational skills are essential qualities. The ideal candidate should have 3 to 5 years of experience in FPGA Development and hold a BE / B.Tech / M.Tech degree in Electronics & Communication Engineering.,

About the Role We are hiring for an Executive Assistant to the founders at Leap. The primary expectation from this role is to provide real leverage to the founders and make sure that they are insanely productive at what they do. Because productive founders set the benchmark for productivity and performance for the company. The charter for this role will include Perform tasks such as managing calendars, planning travel, and other relevant administrative duties. Prompt coordination among various stakeholders for both internal and external meetings. Follow up on action items and ensure timely closure of all actionables. Leading and ensuring the success of vital cross-functional initiatives with multiple stakeholders. Tracking monthly milestones and setting up reviews for the same across all functions. Ideal Persona 2+ relevant years of experience as an EA to the founder or senior leadership team. Extremely resourceful and great at problem solving. Hands-on, adept at multitasking. Exceptional organizational skills and impeccable attention to detail. High degree of professionalism in dealing with diverse groups of people, including Board members, senior executives, internal team, community leaders, donors.

Job Overview: Experience: 3-15 years Responsibilities: Verification engineer with a knowledge of IP verification or SoC integration verification Experience in SoC scenario verification, SoC performance verification, CHI/DDRx/LPDDRx integration verification in SoC RTL. Experience in architecting and implementing SV/UVM testbenches, create and maintain reusable verification components Experience in formal verification strategy for complex IP blocks defining properties, driving proofs and coverage closure Your key responsibilities will include writing test plans, defining test methodologies, SystemVerilog/Verilog testbench development, developing UVM or C based software tests, and debugging of test failures and issues. Working with project management and leads on planning tasks, schedules, and reporting progress Collaborate with engineers from other teams including architecture, design, implementation, modelling, performance analysis, silicon validation, FPGA and board development Required Skills and Experience : Proven understanding of digital hardware verification language Verilog/Systemverilog HDL Experience in SoC verification using Embedded Low-level programming including C/C++ tests and assembly language(preferably ARM) Experienced in one or more of various verification methodologies UVM/OVM, Formal(jasper), power aware verification, emulation Exposure to all stages of verification: requirements collection, creation of verification methodology plans, test plans, testbench implementation, test case development, documentation, and support Good Problem Solving and Debugging skills. Knowledge of IP or SoC Verification Flow and strategy. Experience with ARM-based designs and/or ARM System Architectures. Porting peripheral driver software Clock Domain Crossing verification Experienced in GLS, DFT/DFD, Experienced in UPF Power Aware verification Experience in embedded operating systems, device drivers, microprocessor and embedded system hardware architectures. Automation experience with shell programming/scripting (g. Tcl, Perl, Python etc.) Accommodations at Arm At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Equal Opportunities at Arm

Job Description In your new role you will: Perform Software Development/Validation of device drivers (Eg : MCU, SPI, I2C, CAN, LIN, Ethernet, MEM, Timers, ADC, and PWM etc.) and safety software in an independent/RTOS environment on Infineon s automotive microcontrollers. Evaluate change requests to products, conduct analysis and derive impact for planning by team. Develop architecture, design and code in line with the coding guidelines, safety standards and compliance to MISRA. Develop Test Strategy and institutionalize the methods and related templates to enable the usage of the tools and test equipment wherever required/possible. Envisage, implement, institutionalize and maintain the verification and validation methods and infrastructure (e.g. automation to improve quality and efficiency in terms of cost and time) Your Profile B. Tech/BE/M. Tech/MS in Electrical/Electronics/Computer Science / Telecommunication / Instrumentation. A minimum of 1 to 3 years of experience in Device Driver software development and testing which includes a good know how of standard software development Life Cycle. Experience in AUTOSAR MCAL and exposure to ISO26262 [Expertise in other domains with embedded background more than welcome] Embedded system software development or Validation using C, assembly languages. Experience in the usage of LabView, NI FPGA, oscilloscopes, logic analysers, power benches etc. Experience in embedded system development tools such as compilers, debuggers, static analysers etc. Working experience in scripting languages such as Perl, python, C# etc. Experience in standards such as AUTOSAR, IEC61508, ISO26262 is desirable. Acquaintance with development tool-chains such as GNU, Tasking, and WINDRIVER. Experience in the development/maintenance of the test automation and continuous integration frameworks. Good knowledge of computer architecture (16/32bit), real-time systems. We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant s experience and skills. Learn more about our various contact channels. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon.

S ENIOR SOFTWARE DEVELOPMENT ENGINEER THE ROLE: AMD Datacenter team has an opening for a software Engineer to develop high performance I/O software for compute, storage and network acceleration in hyperscale, virtualized datacenters. Responsibilities include specification and development of Embedded Software for use in Linux and standalone products. This will involve designing and implementing software subsystems to control FPGA Hardware solutions. We are seeking a fast learning, dynamic engineer eager to develop their skills working with the latest FPGA technology. Skills/Experience Experience with C/C++ Experience with Python/System-C is an advantage. Experience with software development in a Linux environment Experience in firmware development, low level driver development, register interface programming, general algorithms and data structures. Experience with industrial standard devices e.g. Ethernet, PCIe, RDMA and Memory architectures DDR/SDRAM/DMA Experience in high performance and low latency, multi-threaded, high throughput SRIOV-capable PCIe-subsystem drivers for compute and network acceleration. Proven track record of delivering software projects that exceed customer quality expectations Experience in successfully executing projects which require interaction with international sites and culturally diverse teams Excellent interpersonal, written and verbal communication skills. A self-starter and team player Iterative Software Development Demonstrates software development skills and proficiency on coding projects within assigned area of responsibility Iteratively codes, debugs, and creates regressions to ensure that code performs as specified with good coverage Documents code to within acceptable standards for the organization Demonstrates a collaborative approach to learning and problem-solving, seeking out and leveraging the talent of others when necessary (e.g. mentoring, code reviews, etc.) ACADEMIC CREDENTIALS: Bachelor s or Master s degree in Computer/Software Engineering, Computer Science, or related technical discipline with 5+ to 12 yrs of experience. #LI-RP1

Full Stack Software Engineer About the Role We are seeking a highly skilled Full Stack Software Engineer to join our team and help us build the next-generation Engagement Portal for our customers. In this role, you will be involved in various aspects of web application development, including frontend user interfaces, backend APIs, database design, authentication systems, real-time collaboration tools, visualization platforms, simulation integration, and performance dashboards. You will work directly with customers at all stages, including onboarding, support, and requirements gathering. This is an exciting opportunity to work in a dynamic environment, involving interaction with our engineering teams, including hardware validation, architecture, design, and software as we build both front-end and back-end systems from the ground up! Our Mission Our aim is to build applications that not only allow our silicon designs to be validated but also provide our customers and partners with a robust platform to kick-start their evaluation of Silicon, allowing them to obtain the highest confidence from design and validation. We are committed to offering "Freedom to Innovate Compute". More about us MIPS is well-known as a microprocessor pioneer, having led the way in RISC-based computing to enable faster and more power efficient semiconductors for a wide range of applications from consumer electronics to networking and communications. More than 30 years after the introduction of the original MIPS RISC architecture, MIPS processors have shipped into billions of consumer and enterprise products. Today, MIPS is once again leading a RISC revolution as we build on our deep roots to accelerate the RISC-V architecture for high-performance applications. We are focused on delivering our first RISC-V products, the MIPS eVocore processors, which provide a new level of scalability for high-performance heterogeneous computing. Because of our RISC heritage, deep engineering expertise, and proven technologies, MIPS can accelerate development and deployment of RISC-V based solutions. At MIPS, you will be a member of a fast-growing team of technologists that are creating the industry`s highest performance RISC-V processors. At MIPS we provide meaningful benefits programs and products to our associates and their families. MIPS offers a competitive benefits package that includes medical, dental, vision, retirement savings, and paid leave! Responsibilities Frontend development and interactive design visualization interfaces Backend API development and other relevant frameworks on cloud and containerized environments Deploying pre-existing validation workflows like simulation result visualization or developing new ones as per customer needs Contribute to the wider silicon validation software ecosystem, helping to ensure support for the platform in various open-source design tools Use tools and real user feedback to analyze and optimize applications, including through the use of performance monitoring and user experience improvements Code-review complex frontend and backend contributions in any of these areas Interact with hardware validation and design teams to improve our next silicon validation platform provide inputs and drive architectural decisions based on user experience needs Help maintain the documentation and reference implementations that our customers rely on Release platform APIs and work with customers to enable integration of their validation workflows for evaluation and development Ideal Candidate Qualifications Experience with full-stack web development Strong JavaScript, TypeScript, or Python programming experience, basic SQL database programming Knowledge of basic web application concepts (e.g., REST APIs, authentication, state management, responsive design) Experience developing user interfaces or backend services in modern frameworks and cloud platforms Proven experience with frontend frameworks (React, Vue.js, Angular, etc.) on different deployment architectures Experience debugging complex web applications Experience with Git, npm, yarn, CI,CD pipelines, and deployment automation scripting Experience with databases, caching, microservices, authentication systems, and application security Experience working with hardware validation and engineering teams Strong communication, collaboration, and listening skills Additional Skills (Nice to Have) Familiarity with silicon design workflows. Knowledge of different EDA tools (e.g., Synopsys, Cadence, Mentor Graphics) Experience working with data visualization and charting libraries (D3.js, Chart.js, Plotly) Some experience working with real-time applications (e.g., WebSockets, real-time collaboration, or streaming data) Any experience with simulation integration or hardware validation automation, FPGA-based validation environments would be very interesting for us

Role & responsibilities Design and Development : Develop and implement FPGA architectures and digital circuits using VHDL or Verilog. Write RTL code and testbenches to meet functional and performance requirements. Perform synthesis, place-and-route, and timing analysis to ensure design closure. Simulation and Verification : Simulate designs using tools like ModelSim, Questa, or Vivado Simulator to validate functionality. Create and execute test plans on hardware test benches to verify FPGA designs. System Integration : Collaborate with hardware, software, and system engineers to integrate FPGA designs into larger systems. Debug and troubleshoot FPGA implementations using tools like logic analyzers, oscilloscopes, and JTAG. Optimization : Optimize FPGA designs for speed, resource utilization, and power efficiency. Ensure signal integrity and timing constraints are met for high-speed interfaces. Documentation : Document design processes, specifications, and test results for compliance and future reference. Participate in design reviews and provide technical input. Continuous Improvement : Stay updated with the latest FPGA technologies, tools, and methodologies. Propose and implement improvements to design workflows and processes. Qualifications and Skills : Education : Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field. Experience : 4-6 years of professional experience in FPGA design, development, and verification. Proven track record of delivering FPGA-based projects from concept to production. Technical Skills : Proficiency in HDL languages (VHDL and/or Verilog/SystemVerilog). Experience with FPGA development tools such as Xilinx Vivado, Intel Quartus, or Microchip Libero. Strong understanding of digital design principles, including timing analysis, signal integrity, and data path optimization. Familiarity with high-speed communication protocols (e.g., PCIe, Ethernet, USB, JESD204B). Experience with simulation tools (e.g., ModelSim, Questa, or VCS). Knowledge of scripting languages (e.g., Python, TCL, or Perl) for automation. Familiarity with embedded systems and hardware-software co-design is a plus. Soft Skills : Strong problem-solving and analytical skills. Ability to work independently and collaboratively in a team environment. Excellent communication skills for technical discussions and documentation Preferred candidate profile Experience in a regulated industry (e.g., aerospace, defence, or medical devices). Knowledge of digital signal processing (DSP) or high-speed digital design. Familiarity with SoC architectures (e.g., Xilinx Zynq, Intel Cyclone) and IP integration. Experience with version control tools (e.g., Git, SVN).

We are seeking an experienced and highly skilled Senior SOC Design for Test Engineer with aminimum of 5 years of hands-on experience in SOC Design for Test. As a key member of our team, you will play a pivotal role in ensuring the testability, manufacturability, and quality of our cutting-edge System on Chip designs Key Responsibilities Lead and manage SOC Design for Test efforts for complex projects, ensuring the successful execution coverage, manufacturability, and quality plans. Develop full chip and block level DFT implementation from the DFx Specifications and product coverage, quality, and manufacturability goals. Define and implement Test controllers at top level and block level, fuse controllers, test clocking strategy, chip I/O test strategy and HSIO test strategy. Define JTAG TAP, boundary scan, I/O Test JTAG access, IEEE1687 iJTAG network and instrument design and implementation. Define the Test Interface for each of the P&R IP blocks for Scan, MBIST and other test interfaces. Define hierarchical block isolation, Test clocking and On Chip Clock controllers and reset methodology. Define scan and MBIST timing at the top level and block level timing. Analyse block level RTL or gates to ensure that scalability and coverage is satisfied as per the design goals. Ensure that DFT is provided to fix the DFT violations to ensure that the design goals are meet. Analyse compression requirements for each of the blocks, define Intest and Extest compression requirements and define the requirements for compression engines. Synthesize compression engines for each of the blocks. Create the collaterals for compression for the IPs. Block level scan insertion as well as development of the scan wrappers for the blocks. Do scan insertion on the blocks, analyse scan DRC, implement DFT fixes. Create scan protocol files for designs, create scan inserted netlist, create scan definitions as well as scan definition files for PD. Perform ATPG on the scan inserted netlist, analyse DRC and coverage violations. Deep knowledge of different scan models Stuck-at, transition test, path-delay, bridging, cell aware, small-delay transition, IDDQ test etc. Ability to analyse coverage for each of the model types. Running GLS with or without timing for the scan vectors. Ability to debug the failures and working with timing and PD teams to fix the timing issues. Understanding of pattern delivery to the post-silicon test engineering teams. Delivering to the Test engineering the Test pin muxing and other full chip requirements for the Test Engineering Team. Understanding tester requirements and delivering the patterns in the formats that the tester teams needs. Implement pattern retargeting. Create grey box models for blocks. Coverage analysis of full chip consolidating Intest and Extest patterns. Knowledge of Top level scan architecture and creating flow to create pattern retargeting. Knowledge of Streaming Scan Network and other Top level scan pin sharing and implementing the block to top level pattern generation for this flow. Implementing Memory Testing and MBIST. Knowledge of Memory defect models and test algorithms. Knowledge of memory bit mapping and redundancy analysis. Implementing memory repair and fuse sharing among various memory. Knowledge of LogicBIST with Test point insertion, X-blocking. Full chip DFT delivery for tapeout including but not limited to DFT netlist verification, pattern delivery, Tester requirements. Debug DFT patterns post silicon, ability to analyse chain test patterns for failures, scan pattern failures. Analyse MBIST pattern failures, yield and repair debug. Ability to perform volume diagnostics on the parts to isolate and improve the patterns. Requirements Bachelors degree in computer science, Electrical/Electronics Engineering, or related field. OR masters degree in computer science, Electrical/Electronics Engineering, or related field. OR PhD in Computer Science, Electrical/Electronics Engineering, or related field. 5+ years of hands-on experience in SOC Design for Test. Expertise in DFT tools and flows in scan intertion, ATPG, GLS simulation, diagnosis flows. Prior experience working on IP level and SOC level DFT projects. Proficient in DFT tools from Siemens (Tessent), Synopsys DFTmax, Tetramax, Spyglass DFT advisor, Genius DFT, Modus, VCS, Xcelium etc. Worked in full chip design or complex IP delivery in the area of DFT. Experience in post silicon debug, diagnosis and yield enhancements is a plus.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: ASIC Design. Experience: 3-5 Years.

This job might be for you if You enjoy solving problems. You love taking on difficult challenges and finding creative solutions. You dont know the answer but will dig until you find it. You communicate clearly. You write well. You are motivated and driven. You volunteer for new challenges without waiting to be asked. You will take ownership of the time you spend with us and make a difference. You can impress our customers with your enthusiasm to solve their issues (and solve them!) Job Description Required Solid RTL coding experience including Microarchitecture of design System Verilog and Verilog coding using provided coding styles. Understanding of SDC Understanding STA reports and how to adjust RTL accordingly. Designing for error cases and debug of IP Understanding of CDC logic Knowledge of lint rules and exceptions Design and use of block level simulations to bring up IP. Knowledge of AMBA buses and when to use them. Job Description Preferred Experienceleading small design team. C coding / Firmware skills Knowledge on common processor architectures(ARM, RiscV) FPGA experience includes part selection, pin assignment, timing constraints, synthesis, and debug of design in the FPGA. Lab brings up experience, scripting. Relevant tool experience such as: Socrates, Core Consultant in additionto standard simulation tools (xcellium, vcs, etc) Emulation experience(Zebu, Palladium, etc) Board knowledge, component selection, probing, debug. JTAG debugging experience (Coresight, Lauterbach, etc). Low power design techniques Qualifications E./B.Tech. degree at minimum.

You will be joining Silicon Labs, a leader in secure, intelligent wireless technology known for its integrated hardware and software platform, intuitive development tools, and robust support. As a part of the Digital Architecture team, you will be involved in the research and development of digital architecture and IPs, covering compute engines, processors, audio and video subsystems, accelerators, peripherals, and system IP. Your role will focus on designing and implementing scalable and innovative digital architectures to support the business objectives of providing power-efficient solutions for low-power embedded wireless devices. Your responsibilities will include leading the evaluation and selection of digital technologies, collaborating with stakeholders to understand requirements, ensuring the security and reliability of digital systems, and providing technical leadership to developers and junior architects. You will also need to stay updated with industry trends and emerging technologies to drive innovation and effectively document and communicate architectural solutions. To be successful in this role, you should have demonstrated experience in defining and designing high-complexity designs, excellent understanding of embedded systems, and strong communication skills. Additionally, you should possess knowledge in low power design, HDL-based RTL logic design, front-end design tools, and debugging in simulation, FPGA, and silicon environments. Preferred experience in the design of microprocessors, math-centric designs, high-level software languages for modeling, and scripting skills will be advantageous. In return, you will not only work in a collaborative and learning-driven team but also enjoy benefits such as equity rewards, insurance plans, flexible work policy, and childcare support. If you are looking to relocate to HYDERABAD and want to be a part of a team that values innovation, simplicity, quality, and smart development processes, we encourage you to apply for the Staff Digital Architect position at Silicon Labs.,

MTS SOFTWARE DEVELOPMENT ENGINEER THE ROLE: Ideal candidate should have 7 to 12 years of experience in technical roles involving tool development with some focus in areas of regression management like scheduling, executing harness, failure analysis & assignment and reporting. Also should have hands-on experience in working with DevOps env tools including cloud, databases & AI/ML technologies. THE PERSON: The ideal candidate should be passionate about software engineering and possess leadership skills to drive sophisticated issues to resolution. Able to communicate effectively and work optimally with different teams across AMD. KEY RESPONSIBILITIES: Drive and improve implementation of test infrastructure to provide robust test environment to developers & testers Analyze, optimize & improve current architecture of various components of test Infra tools including integration Implement containerized test infra with full on-prem/cloud portability Compatible with various job management systems like LSF, SLURM, and Kubernetes orchestration framework Drive & Implement strategies to leverage AI/ML models at various stages of testinfra Drive & Implement Next Gen QOR (Quality of results for FPGA designs) regression execution & reporting Overseeing and providing development support to team members. Collaborating with cross-functional teams, providing technical support, and troubleshooting migration to next generation tools, CI/CD, containerization, Kubernetes, and cloud tooling issues. Creating comprehensive documentation, mentoring junior team members, and conducting training sessions PREFERRED EXPERIENCE: Professional 8+ yrs of technical experience and at least 5 years experience in design & implementation of product developments Strong knowledge in CI/CD tools and DevOps practices. Experience in developing tools around test Infra automation Expert in structured & OOP in Python Proficiency in Scripting and automation languages (e.g., Python, Bash, Csh,..) Linux & Windows shells working environment Understanding of AI/ML principles and some experience in applying LLM & ML models in tool development Experience with working in DevOps environment like GitHub, Perforce version control systems, containerization technologies like Docker, Kubernetes orchestration and CI/CD pipelines using Jenkins or Github actions Additionally, experience with monitoring and logging tools for containerized environments (e.g., Prometheus, Grafana) Excellent problem-solving abilities with a keen eye for detail are highly valued ACADEMIC CREDENTIALS: Bachelor s or Masters degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent. #LI-RP1

We are looking for a seasoned Senior Design Verification Engineer with 8+ years of experience in verifying complex digital IPs and SoCs. The ideal candidate will have strong expertise in developing UVM-based verification environments and driving functional coverage closure. Key Responsibilities: Develop and maintain constrained-random and directed testbenches using System Verilog/UVM Define verification plans and test strategies based on specifications Write test cases, checkers, and functional coverage models Perform RTL simulations, debug failures, and ensure coverage closure Collaborate with RTL, DV, and firmware teams across verification lifecycle Support gate-level simulation, regression management, and post-silicon bring-up Requirements : 8+ years of hands-on experience in digital design verification Expertise in System Verilog, UVM, and verification methodology Strong debugging skills using simulators like VCS, Questa, or Incisive Good understanding of protocols like AMBA (AXI/AHB/APB), PCIe, Ethernet, etc. Experience with coverage tools, version control, and regression systems Strong communication, collaboration, and documentation skills

As a Logic design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers.Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLLAdditional responsibilities:logic (RTL) design, timing closure, CDC analysis etc.Understand and Design Power efficient logic.Agile project planning and execution.RequirementsMasters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Minimum 8+ years of experience in Chip design and development. Understand CPU / GPU / RISC V architectures. Expertise in one of the architecture and design of Core units (Fetch, Decode, arithmetic units -adders, multipliers, L1/L2/L3 cache , Mem , IO ) Understand RISC V core Experience with VLSI Design in VHDL / Verilog

Design and development of processor L2 , L3, Non cacheable units and LLC (Last Level Cache) for high-performance IBM Systems. - Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements. - Develop the features, present the proposed architecture in the High level design discussions - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature. . Required education Master's Degree Preferred education High School Diploma/GED Required technical and professional expertise 8 to 15 years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design,

The Technical Support Engineer role of the z/OS support team involves supporting components of z/OS operating system in mainframe. This position will be to help design and execute productivity aids required for the infrastructure. Some programming skills are required and a basic engineering understanding to perform this role. Computer Science skills are highly desired. Technical Support Engineer will have the opportunity to experience firsthand what a mainframe customer expects from IBM as well as the technical complexity of this machine. Required education Bachelor's Degree Required technical and professional expertise Passion to pursue career path in Computer Engineering or Computer Science Fundamental education in software design and/or test Computer Architecture Knowledge of any programming languagesC, C++, Java, Assembly Good debugging skills Scripting knowledgePython, JavaScript, Perl, Bash, etc Strong Communication Skills Preferred technical and professional experience Development knowledge of Unix/Linux kernel functionality Knowledge of LAN drivers FPGA experience Experience in embedded systems development Knowledge of web and mobile application development Tools (Git/GitHub, IntelliJ, etc.)

As a Logic design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL/Test Pervassive Additional responsibilities: logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. RequirementsMasters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise -8+ years of relevant experience - At least 1 generation of processor core/cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.