About The Role : Builds emulation and FPGA models and solutions from RTL design using synthesis, partitioning, and routing tools. Develops, integrates, tests, and debugs hardware and software collateral in simulation, emulation, and FPGA models for testing new features, writes directed tests, develops the test environment and hybrid emulation environment, and supports verification of hardware and software/firmware. Defines and develops new capabilities and tools to achieve better verification through improved emulation and FPGA model usability. Enables acceleration of RTL development and improve emulation/FPGA model usability for presilicon verification, postsilicon validation, and software development. Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform and interfaces with and provides guidance to verification teams for optimizing presilicon verification environments, test suites, and methodologies for emulation efficiency. Develops and utilizes automation aids, flows, and scripts in support of emulation utilization. Applies understanding of emulation and FPGA prototyping tools and methodologies, SoC integration, emulation transactors, emulation performance and optimization techniques, RTL simulation, and hybrid emulation environments (virtual platform and FPGA/emulation model). Collaborates with design, power and performance, silicon validation, and software teams, and participates in SoC and IP bring up, root causes testbench issues, IP and SoC testcases, and emulator/FPGA environment issues. Qualifications Bachelor Degree in Electrical and Electronics Engineering or Master's Degree in Electrical and Electronics Engineering or Computer Engineering with 8+ years experience. Experience in Pre-si/post-Si validation with FPGA based validation, Experience with bring up of functional tests on FPGA/Si. Experience in Hardware validation/emulation platforms like zebu, veloce or functional bring up of PM/Reset/PCIE/DMI/DDR/Mem et.al. Good understanding of SoC architecture / uArchitecture, Networking protocols or Signal processing algorithms/flows in hardware. Excellent understanding of test framework and abstraction, develop test plans, test scripts for functional validation. Very good debugging skills, experience of working with various hardware debugging tools JTAG, Verdi, fsdb analysis. Good knowledge in C/C++, Scripting knowledge (Python/Perl/Tcl), ability to develop parsers. Knowledge in RTL design, VHDL/Verilog is a plus. Strong analytical ability, problem solving and communication skills. Ability to work independently and at various levels of abstraction. Inside this Business Group The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers. Working Model This role will require an on-site presence. *

Role & responsibilities Proficiency in PCB design tools (e.g., Altium Designer, Cadence, Mentor Graphics). Strong knowledge of signal integrity, power integrity, and EMI mitigation techniques. Experience with high-speed interfaces (e.g., DDR, PCIe, USB, Ethernet, LVDS, MIPI). Hands-on experience with lab testing and debugging high-speed circuits. Familiarity with FPGA/ASIC design workflows is a plus. Power Circuit Proficiency in power electronics design tools (e.g., Altium Designer, Cadence Allegro, PSpice). Strong understanding of SMPS, AC/DC, and DC/DC conversion topologies (Buck, Boost, Flyback, LLC, etc.) Experience in designing circuits for high-power applications (e.g., 100W - 10kW power range). Hands-on experience with lab testing and troubleshooting power circuits. Familiarity with microcontrollers, DSPs, or FPGA-based power control Required Skills Hands- on experience in Analog/ Digital / Mixed signal & RF Circuit Design. Experience in the hardware design, development and testing of high speed digital electronic circuits including microprocessors, microcontrollers, FPGA and embedded firmware. Experience in product design, board level testing, integration and validation testing including development of test plans and Pass/fail criteria. Strong knowledge of using Design and simulation tools Experience of Hardware Verification to comply to IEC 60601 standards Excellent troubleshooting skills on Electrical / Electronic boards to find the root cause and to propose the best solution Experience of working with multi-disciplinary team ( Mechanical, PCB layout, Systems engineering and suppliers) Should have an understanding and use of DFMEA, DFT and DFM tools Definition and choice of components (including derating) Experience in FPGA , DSP and 8/16/32 bit Micro-controller-based circuit design. Hands- on experience in the usage of CRO , function generator and other electronic analysis and testing tools. Understanding of PCB design guidelines , EMI/EMC testing would be an added advantages.

Role Power platform developers Location Pune Must have skills 4 to 10 yrs experience Power Apps Power Automate Developer Working knowledge on SQL Server database Should have worked on Power Apps with SQL Server as data source At least 3 years experience in Power Apps With selflearning attitude if good in Power Apps but lack knowledge in SQL Server Must have soft skills Good communication skills Solutioning attitude Excellent interpersonal skills Need can do attitude

Design next-generation HW features in partnership with front-end teams and industry partners Drive feature and cost trade-off analysis to provide technical recommendations Provide design guidance to enable and support global teams Deliver assigned system interfaces with design and process across extended teams Prepare documentation for inspection/testing procedures Take the first step towards your dream career Every Dell Technologies team member brings something unique to the table. Here s what we are looking for with this role: Essential Requirements 8-12 years of experience in systems design and architecture with Verilog coding, System Verilog, and VHDL coding practices. Experience in digital design methods such as CDC (Clock Domain Crossing), RDC (Rest Domain Crossing), timing constraints definition, and static timing analysis. Experience in RTL Design Digital Design Principles and x86 Core or ARM processor architecture. Experience in Peripheral Protocols like I2C, I3C, SMbus, IPMI, IPMB Strong fundamentals in both analog and digital design practices with a desire to share knowledge and mentor others Experience and deep knowledge of hardware and software interactions, and ability to apply this understanding to resolve issues. Desirable Requirements Experience in x86(AMD Intel) and ARM architecture. Experience with FPGA development tools like XILINX, Lattice, and Altera Quartus. (Modelsim/QuestaSim)

About The Role : The world is transforming - and so is Intel. Here at Intel, we believe the world needs technology that can enrich the lives of every person on earth. We work every single day to design and manufacture silicon products that empower peoples digital lives. Do you love to solve technical challenges that no one has solved yet? Do you enjoy working with cross functional teams to deliver solutions for products that impact customers lives? If so, Come join us to do something wonderful.Your responsibilities will include but not limited to:Oversees definition, design, verification, and documentation for SoC (System on a Chip) development. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Performs Logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs. Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Performs all aspects of the SoC design flow from highlevel design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing. Analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results. May also review vendor capability to support development. Qualifications You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications Candidate will have a Bachelors degree in Computer Engineering/ Computer Science or Electrical Engineering with 6+ years of experience -OR- a Masters degree in Computer Engineering Computer Science or Electrical Engineering with 4+ years of experience with C and Object Oriented Software design including algorithms and data structures Knowledge of Software development practices and quality standards Experience with Unix Windows based SW development tools . Experience developing bus functional models for unit level verification or Verification IP development Preferred Qualifications Proficiency in System C SystemVerilog UVM and ESL modeling methodologies Proficiency in HW design and verification methodologies Working knowledge of highspeed HW protocols eg PCIe UPI DDR Inside this Business Group The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies"”spanning software, processors, storage, I/O, and networking solutions"”that fuel cloud, communications, enterprise, and government data centers around the world.

About The Role : Conducts verification of IP and/or SoC microarchitecture using formal verification tools, methodologies, and technologies based on model checking and equivalence checking algorithms. Creates comprehensive formal verification test and coverage plans to include definition of formal verification scope, strategy, and techniques. Creates abstraction models for convergence on the design, carves out the right boundaries for the design, and tracks, verifies, and applies abstraction techniques. Develops formal proofs to implement the verification plan, reviews the completed proofs, and develops new formal verification methodologies. Performs convergence on design by creating formal verification methodology, abstraction, and simulation techniques. Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Qualifications M Tech with 7+ years of experience B Tech with 8+ years of experience. Electrical and Electronics or Communication Engineering Hands on Experience on verification of IPS Min 2 years hands on experience on formal verification Inside this Business Group The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies"”spanning software, processors, storage, I/O, and networking solutions"”that fuel cloud, communications, enterprise, and government data centers around the world. Working Model This role will require an on-site presence. *

Job title: FPGA Architect (Telecom/Aerospace) Reporting Relationship: Reporting to Project Manager Job Summary: NEC Corporation India Pvt. Ltd is looking for an experienced and highly talented FPGA Architect with strong telecom or aerospace expertise at NEC Mobile Network Excellence Center (NMEC), Chennai Scope of work System modeling, architecture, and implementation of high-performance FPGA designs for wireless communication and aerospace system Conducting research and development of logical synthesis, netlist partitioning, placement, and routing optimizations for FPGA prototyping. Optimize FPGA designs for latency, throughput, power, performance, and area efficiency Evaluate and select appropriate technologies and tools to support the development process Work with cross-functional teams to align on product requirements and technical specifications. Qualifications BE/B.Tech/M.E/M.Tech or its Equivalent Experience 12+ years Domain skills Strong knowledge of SoC architecture, including CPU, GPU, memory hierarchy, interconnects, and accelerators. Hands-on experience in hardware simulators, SoC design (SoC integration, peripherals, bus design, RTL coding in Verilog/VHDL, CDC, LINT) Experience in RTL coding, synthesis, place-and-route, STA, power analysis, back-end flow, implementing designs in hardware, and advanced digital verification methodology(UVM) Prior experience in integrating Nios, MPIS, MicroBlaze, ARM Cortex, GTX/GTH transceivers, and 10GE MAC/DMA controller/PCIe /CPRI/JESD/FFT IP core. Knowledge of AXI/AHB AMBA bus-based complex multi-master and slave systems, L2/L3 switching, TCP/IP, and network protocols. Experience with EDA tools such as Xilinx Vivado, SystemGenerator, ModelSim/QuestaSim. Proficiency in MATLAB and Python for modelling, simulation, and analysis. Specialization Description Responsible for improving or developing new products, components, equipment, systems, technologies, or processes including: Ensuring that research and design methodologies meet established scientific and engineering standards Assisting with formulating business plans and budgets for product development Analyzing quality/safety test results to ensure compliance with internal and external standards Keeping abreast of new developments in the industry and translating those developments into new and viable options for the organization and customers Organizing technical presentations to customers and/or industry groups Monitoring product development outcomes to ensure technical, functional, cost, and timing targets are met In some organizations, may be responsible for managing product regulatory approval process Level Description Senior level professional that applies advanced knowledge of job area typically obtained through advanced education and work experience. Works independently applying an advanced knowledge of a job area typically obtained through advanced education and work experience. Works to achieve results in a job area, overseeing and managing projects/ processes independently with limited supervision. Problems faced are difficult and are sometimes complex, though are routine. Coaching and reviewing the work of lower level professionals. Headquartered in Japan, NEC is a leader in the integration of IT and network technologies. With over 123 years of expertise in providing solutions for empowering people, businesses, and society, NEC stands tall as a champion in enabling change and transformation across the globe. Present in India since 1950, NEC has been instrumental in burgeoning India s digitization journey continually for the past 70 years. NEC India has proved its commitment to orchestrating a bright future through its diverse businesses from Telecommunications to Public Safety, Logistics, Transportation, Retail, Finance, Unified Communication and IT platforms , serving across the public and private sectors. NEC India, through the deployment of cutting-edge technology, has been powering India in seminal ways, making lives easier, safer, and more productive for all. With its Centre of Excellence for verticals like Analytics platform solutions, Big Data, Biometrics, Mobile and Retail , NEC India brings to the table, innovative, seamless solutions for India and across the world. NEC India is headquartered in New Delhi and has its offices panned across the country. It has branches in Ahmedabad, Bengaluru, Chennai, Mumbai, Noida and Surat. Specialties: IT Networking Solutions, Unified Communication Solutions, Safety and Security Solutions, Integrated Retail Solutions, Data Centre Solutions, Safe and Smart City Solutions, Transportation Solutions, SDN Solutions, Carrier Telecom Solutions, and Solutions for Society. NEC Career Site - LinkedIn

Job title: Hardware solutions Architect (Telecom/Aerospace) Reporting Relationship: Reporting to Project Manager Job Summary: NEC Corporation India Pvt. Ltd is looking for an experienced and highly talented Hardware architect with strong telecom and datacom expertise to support the architecture definition, high level design and development guidance activities at NEC Mobile Network Excellence Center (NMEC), Chennai. Knowledge in aerospace domain is an added benefit. Scope of Work Support in requirement gathering from customer and defining the specification Co-ordinate with system team for deriving the system/HW architecture Support team in HFS, detailed design and development. Support development activities like PCB input and reviews, power supply design, BOM, stack up, etc. Co-ordinating with cross functional team like diagnostics, SI/PI, mechanical, thermal, FPGA, RF etc. Provide guidance for Board bring up, interface testing, design validation etc. Support regulatory and compliance testing specification. Support for Proto/Pilot and mass production. Interaction with various vendors/ OEMs to identify more optimized solutions. Supporting quality team to adhere to standards. Qualifications BE/B.Tech/M.E/M.Tech or its Equivalent Experience 14+ years Domain skills Strong experience in defining the HW architecture in co-ordination with system team Strong Hardware Design Capabilities for networking product design Experience in handling processor-based design, SoC, ASIC, FPGA and network related components. Experience in Handling Complete Product Design Life Cycle Good hands-on experience in High speed design like DDR5, LPDDR4, DDR4, PCIe, XAUI, RXAUI, XFI, SFI, XLAUI, SFP28, EMMC, Ethernet SGMII, RGMII, USB 3.0, eCPRI, JESD204, JTAG etc Strong debugging capabilities involving FPGA, processor, ASIC, analog and digital domain. Good command over timing solutions like syncE and 1588 . Sound and hands-on experience in Product Compliance/Regulatory standards and testing Experience in Analog, Digital, and Mixed-signal board design Experience in board bring up and supporting diagnostic team Knowledge of Schematic PCB design tools like Cadence Hands-on experience in usage of HW tools like Oscilloscope, Signal analyzer, Network analyzer, Spectrum analyzer, etc. Specialization Description Responsible for improving or developing new products, components, equipment, systems, technologies, or processes including: Ensuring that research and design methodologies meet established scientific and engineering standards Assisting with formulating business plans and budgets for product development Analyzing quality/safety test results to ensure compliance with internal and external standards Keeping abreast of new developments in the industry and translating those developments into new and viable options for the organization and customers Organizing technical presentations to customers and/or industry groups Monitoring product development outcomes to ensure technical, functional, cost, and timing targets are met In some organizations, may be responsible for managing product regulatory approval process Level Description Senior level professional that applies advanced knowledge of job area typically obtained through advanced education and work experience. Works independently applying an advanced knowledge of a job area typically obtained through advanced education and work experience. Works to achieve results in a job area, overseeing and managing projects/ processes independently with limited supervision. Problems faced are difficult and are sometimes complex, though are routine. Coaching and reviewing the work of lower level professionals. Headquartered in Japan, NEC is a leader in the integration of IT and network technologies. With over 123 years of expertise in providing solutions for empowering people, businesses, and society, NEC stands tall as a champion in enabling change and transformation across the globe. Present in India since 1950, NEC has been instrumental in burgeoning India s digitization journey continually for the past 70 years. NEC India has proved its commitment to orchestrating a bright future through its diverse businesses from Telecommunications to Public Safety, Logistics, Transportation, Retail, Finance, Unified Communication and IT platforms , serving across the public and private sectors. NEC India, through the deployment of cutting-edge technology, has been powering India in seminal ways, making lives easier, safer, and more productive for all. With its Centre of Excellence for verticals like Analytics platform solutions, Big Data, Biometrics, Mobile and Retail , NEC India brings to the table, innovative, seamless solutions for India and across the world. NEC India is headquartered in New Delhi and has its offices panned across the country. It has branches in Ahmedabad, Bengaluru, Chennai, Mumbai, Noida and Surat. Specialties: IT Networking Solutions, Unified Communication Solutions, Safety and Security Solutions, Integrated Retail Solutions, Data Centre Solutions, Safe and Smart City Solutions, Transportation Solutions, SDN Solutions, Carrier Telecom Solutions, and Solutions for Society. NEC Career Site - LinkedIn

Job title: FPGA Lead (Telecom/Aerospace) Reporting Relationship: Reporting to Project Manager Job Summary: NEC Corporation India Pvt. Ltd is looking for an experienced and highly talented FPGA Lead with strong telecom or Aerospace expertise at NEC Mobile Network Excellence Center (NMEC), Chennai Scope of work Implementing FPGA code on the target hardware testing with other system components and software RTL Design, Implementation, Testing, Integration and delivery of FPGA based hardware systems for Telecom and Aerospace Applications Interaction with various vendors/ OEMs to identify the right solution Cowork with internal/external engineering team on Hardware, RF, Mechanical and Software team etc. Qualifications BE/B.Tech/M.E/M.Tech or its Equivalent Experience 8+ years Domain skills Expert in FPGA flows with Xilinx, including compilation, synthesis, debug, performance and implementation of advanced features Good Hands on Linting, Static Timing Analysis, Equivalence Checking Clock Domain Crossing. Experience in developing verification environment to verify developed items using self-checking test benches, BFMs, checkers/Monitors Score boards using VHDL/verilog. Prior experience in integrating Nios, MPIS, MicroBlaze, ARM Cortex, etc. GTX / GTH transceivers 10GE MAC / DMA controller / PCIe Gen3 / CPRI / JESD / FFT IP core Common control interfaces design, like AMBA AXI, UART, SPI, I2C, DDR, Ethernet, USB, etc.. Knowledge on programming languages such as Verilog, VHDL and system Verilog Experience with any scripting language for automation (Perl/TCL/Python). Familiar with standard FPGA HW bring-up activities and testing Experience with HW measuring tools like oscilloscopes, Signal analysers, JTAG Emulators Specialization Description Responsible for improving or developing new products, components, equipment, systems, technologies, or processes including: Ensuring that research and design methodologies meet established scientific and engineering standards Assisting with formulating business plans and budgets for product development Analyzing quality/safety test results to ensure compliance with internal and external standards Keeping abreast of new developments in the industry and translating those developments into new and viable options for the organization and customers Organizing technical presentations to customers and/or industry groups Monitoring product development outcomes to ensure technical, functional, cost, and timing targets are met In some organizations, may be responsible for managing product regulatory approval process Level Description Experienced level professional that applies practical knowledge of job area typically obtained through advanced education and work experience. Works independently with general supervision. Works to achieve operational targets within the job area with a direct impact on function / sub-function results. Problems faced are difficult but typically not complex. May influence others within the job area through explanation of facts, policies and practices. Headquartered in Japan, NEC is a leader in the integration of IT and network technologies. With over 123 years of expertise in providing solutions for empowering people, businesses, and society, NEC stands tall as a champion in enabling change and transformation across the globe. Present in India since 1950, NEC has been instrumental in burgeoning India s digitization journey continually for the past 70 years. NEC India has proved its commitment to orchestrating a bright future through its diverse businesses from Telecommunications to Public Safety, Logistics, Transportation, Retail, Finance, Unified Communication and IT platforms , serving across the public and private sectors. NEC India, through the deployment of cutting-edge technology, has been powering India in seminal ways, making lives easier, safer, and more productive for all. With its Centre of Excellence for verticals like Analytics platform solutions, Big Data, Biometrics, Mobile and Retail , NEC India brings to the table, innovative, seamless solutions for India and across the world. NEC India is headquartered in New Delhi and has its offices panned across the country. It has branches in Ahmedabad, Bengaluru, Chennai, Mumbai, Noida and Surat. Specialties: IT Networking Solutions, Unified Communication Solutions, Safety and Security Solutions, Integrated Retail Solutions, Data Centre Solutions, Safe and Smart City Solutions, Transportation Solutions, SDN Solutions, Carrier Telecom Solutions, and Solutions for Society. NEC Career Site - LinkedIn

Job Description: Should be having hing level understanding for Design, develop and test various types of antennas for various applications. Conduct research and evaluate the performance of novel antenna design CST/ HFSS/ MATLAB software skills are preferred Develop and maintain technical documentation, including test plans and reports Should have knowledge related to fabrication and testing of the designed antenna. Good communication and analytical problem solving capability. Hands-on experience on FPGA / RTL Design involving verilog HDL,Cadence, Vivado ISE/Xilinx ISE, Modelsim and Synopsys will be an added advantage.

Builds emulation and FPGA models and solutions from RTL design using synthesis, partitioning, and routing tools. Develops, integrates, tests, and debugs hardware and software collateral in simulation, emulation, and FPGA models for testing new features, writes directed tests, develops the test environment and hybrid emulation environment, and supports verification of hardware and software/firmware. Defines and develops new capabilities and tools to achieve better verification through improved emulation and FPGA model usability. Enables acceleration of RTL development and improve emulation/FPGA model usability for presilicon verification, postsilicon validation, and software development. Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform and interfaces with and provides guidance to verification teams for optimizing presilicon verification environments, test suites, and methodologies for emulation efficiency. Develops and utilizes automation aids, flows, and scripts in support of emulation utilization. Applies understanding of emulation and FPGA prototyping tools and methodologies, SoC integration, emulation transactors, emulation performance and optimization techniques, RTL simulation, and hybrid emulation environments (virtual platform and FPGA/ emulation model). Collaborates with design, power and performance, silicon validation, and software teams, and participates in SoC and IP bring up, root causes testbench issues, IP and SoC testcases, and emulator/FPGA environment issues. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: B.E/B.Tech(ECE/VLSI) B.Tech or M.Tech with 2 to 8 yrs of hands on experience. Emulation Test development with debug OR emulation model build. Hands on in Zebu and verilog coding. Preferred Qualifications: M.E/M.Tech Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/ classes/research.

Senior Software Engineer The Software Engineering team delivers next-generation application enhancements and new products for a changing world. Working at the cutting edge, we design and develop software for platforms, peripherals, applications and diagnostics all with the most advanced technologies, tools, software engineering methodologies and the collaboration of internal and external partners. Join us to do the best work of your career and make a profound social impact as a Senior Software Engineer on our Software Engineering Team in Bangalore. What you ll achieve As a Senior Software Engineer, you will be responsible for developing sophisticated systems and software basis the customer s business goals, needs and general business environment creating software solutions. You will: Contribute to the design and architecture of new or re-engineered software/storage environments Prepare written software/storage specifications for sophisticated products from architectural diagrams and documents Build and review design, functional, technical and/or user documentation, as needed Develop, review and implement test strategies for software products and systems Take the first step towards your dream career Every Dell Technologies team member brings something unique to the table. Here s what we are looking for with this role: Essential Requirements 5-8 years of software development experience Strong firmware / System development background with strong C/C++ development/debug skills and Strong in Embedded Linux programming, OS Internals, memory management, IPC, thread programming, and embedded application software development. C++, IPMI, DMTF, RedFish, CIM, CIMOM, Linux. Solid understanding of SNMP, and IPMI protocols. Experience/exposure to I2C, MCTP, NCSI, PLDM, and uEFI protocol is a plus. Working experience with peripheral hardware devices like PCIe Switch, NIC, GPU, FPGA, Memory Controllers, etc. is a plus. Very good server system architecture understanding along with Power and Thermal domain expertise. Desirable Requirements Bachelor s degree/ Masters degree

About The Role : Conducts verification of IP and/or SoC microarchitecture using formal verification tools, methodologies, and technologies based on model checking and equivalence checking algorithms. Creates comprehensive formal verification test and coverage plans including definition of formal verification scope, strategy, and techniques. Creates abstraction models for convergence on the design, carves out the right boundaries for the design, and tracks, verifies, and applies abstraction techniques. Develops formal proofs to implement the verification plan, reviews the completed proofs, and develops new formal verification methodologies. Performs convergence on design by creating formal verification methodology, abstraction, and simulation techniques. Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Understands the binary decision diagram (BDD) and data flow graph (DFG) for data paths and resolves the BDD complexity on arithmetic. Applies understanding of modeling architecture to simplify and model the problem and uses tools to formally prove protocols and architectures. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: 9+ years of experience in the verification of IPs - This is a leadership role in which a good understanding of common microarchitectures designs is needed Hands on experience in applying formal property verification for Ips signoff at least for 3 years Hands on experience in resolving convergence issues using FV on multiplies- Good handle on FV verification strategy and design partitioning for better convergence. Managing and Guiding juniors in their verification task Stakeholder management - Multiproject tracking and execution Preferred Qualifications: Expertise in FV verification planning and strategies. Good understanding of FV tools and capabilities. Inside this Business Group In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel's products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore's Law and groundbreaking innovations. DEG is Intel's engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

About The Role : The Client Development Group (CDG) is looking for a highly motivated SOC/IP RTL Design Engineer Lead to join the client SOC frontend design and integration team for the next generation of Client SOC. In this role, the candidate's responsibilities include, although not limited to: Understand IP and SOC arch/urach requirements for building client SOC, understand the global flows like clock, power delivery, design for debug (DFD) etcFamiliar with IP/SOC design tools, flows and methodology. Familiar with all aspects of the SoC/IP design flow from high-level design to synthesis, timing and power to create a design database that is ready for manufacturing. Have thorough understanding of design quality requirements for delivering a robust and scalable IP. Perform integration of functional units and subsystems into SoC full chip. Have good understanding of uarch concepts and RTL coding . Run, analyse and fix various quality check tools and flows such as CDC, lint, VCLP, etc. Define power domains using UPF and hit performance, power and area targets. Work with backend engineers on pre and post physical design timing closure. Work with verification engineering to debug test cases in RTL and Gate Level simulation environment. Work with cross-functional teams to make sure designs are delivered on time, and with highest quality, by incorporating proper checks at every stage of the design process. As a lead, set priorities for the team, get results across boundaries, ensure an inclusive work environment, develop employees. Qualifications Bachelor's in Electrical/ Computer Engineering, Computer Science or related field plus 8+ years of relevant experience. OR a Master's degree in Electrical/Computer Engineering, Computer Science or related field with 6+years of relevant experience. ( Years of Experience updated) Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

About The Role : Do Something Wonderful. Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow. Come join us -- Who We Are In this role you will be part for the Server SoC Design Validation team, working on next-generation Xeon server product SOCs and IPs. Who You Are Your responsibilities include but are not limited to: Performs functional logic verification and emulation validation of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, micro-architects, full chip architects, RTL developers, post-silicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from post-silicon on the quality of validation done during pre-silicon development, updates test plan for missing coverages and proliferates to future products. Behavioral traits that we are looking for: Robust understanding of fundamental principles of cache coherency in multi-processor SOCs, and experience with layered protocols - transaction layer, data link layer, and PHY layer. Strong debug skills and self-reliance in taking an issue to closure with internal and external partners. Takes ownership of assigned tasks. Keen problem solver, strong communicator, quick learner, effective team player and open to learning and teaching new and more efficient validation execution techniques to meet time-to-market. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 8+ years of technical experience Related technical experience should be in/with:Silicon Design and/or Validation/Verification. Preferred Qualifications: Design and/or Design Verification with developing, maintaining, and executing complex IPs and/or SOCs. OVM/UVM, System Verilog, constrained random verification methodologies. The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure). Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies. Experience in Xeon CPU Pre-Silicon or Post Silicon Validation. Experience on Pre-Si validation on Emulation, preferably Zebu.Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research. Inside this Business Group The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies"”spanning software, processors, storage, I/O, and networking solutions"”that fuel cloud, communications, enterprise, and government data centers around the world.

Responsibilities Candidate should have experience in software development role, tools development, firmware development or validation tools development. Candidate shall design and develop algorithms for Post Silicon Validation of next generation IBM server processors, SOCs and ASICs. He will be the key interface on processor Bringup Activities and own key debugs of architecture and micro-architecture issues during the bring up/power on phase. The candidate will be expected to interface with multiple stakeholders in hardware design teams, lab teams, performance teams and characterization teams. Candidate must drive coverage closure by developing comprehensive test plans and strategies and drive to achieve coverage goals while interacting with stakeholders, verif teams and design teams. He/She must be skilled in utilizing object-oriented programming skills in C/C++ and scripting languages like Python/Perl to write complex test scenarios to automate/optimize. Candidate must possess experience in verifying multi-processor cache coherency and memory subsystems, ensuring seamless operation in complex systems. Proficiency in emulator env/FPGA validation is preferred. She/he must possess excellent communication skills and understand agile processes. The candidate must have an eagerness and curiosity to learn and be willing to code and participate hands on. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Technical Expertise:Very proficient in C programming, Strong Scripting skills. Over 10 years experience in hands on Software development using C, C++. Computer Architecture Knowledge:In-depth knowledge of computer architecture, including processor core design specifications, instruction set architecture, and logic verification. Multi-Processor Cache Coherency:Experience in verifying multi-processor cache coherency and memory subsystems, ensuring seamless operation in complex systems. Operating Systems and Concepts:Atleast 5 years experience with Multithreading, context switching, memory management related development Preferred technical and professional experience IO device drivers, firmware exposure(NIC controller, PCIe device controllers, ASIC FW development experience) ARM architecture RISC V architecture Spike simulator experience, QEMU simulator

Responsibilities As a Logic design lead in the IBM Systems division, you will be responsible for the micro architecture, design and development of a high-bandwidth, low-latency on-chip interconnect (NoC) and chip-to-chip interconnect and integration into high-performance IBM Systems. Design and architect different interconnect topologies as driven by bandwidth, latency and RAS requirements Develop the features, present the proposed architecture in the High level design discussion Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, FW, SW teams to develop the feature Signoff the Pre-silicon Design that meets all the functional, area and timing goals Participate in silicon bring-up and validation of the hardware Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 12+ years of relevant experience - At least 1 generation of processor interconnect design delivery leadership (eg UPI, axi, amba, NoC). - Expertise of SMP coherency - Experience in different on-chip interconnect topologies (e.g., mesh, crossbar) - Understanding of various snoop and data network protocols - Understanding of latency & bandwidth requirements and effective means of implementation - Working knowledge of queuing theory - numa/nuca architecture - Proficient in HDLs- VHDL / Verilog - Experience in High speed and Power efficient logic design -Experience in working with verification, validation, physical design teams for design closure including test plan reviews and verification coverage - Good understanding of Physical Design and able to collaborate with physical design team for floor planning, wire layer usage and budgets, placement of blocks for achieving high-performance design - Experience in leading uarch, RTL design teams for feature enhancements. Preferred technical and professional experience - Follow agile project leadership principles. Work with the team on estimation and execution plan. - Ability to quickly understand issues spanning multiple functional domains, switch context frequently and provide solutions to problems, is necessary.

Responsibilities As a Logic design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL Additional responsibilities: logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. Requirements:Masters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Minimum 5+ years of experience in Chip design and development. Understand CPU / GPU / RISC V architectures. Expertise in one of the architecture and design of Core units (Fetch, Decode, arithmetic units -adders, multipliers, L1/L2/L3 cache , Mem , IO ) Understand RISC V core Experience with VLSI Design in VHDL / Verilog

Responsibilities -Lead the Architecture, Design and development of processor L2 and LLC (Last Level Cache) for high-performance IBM Systems. - Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements. - Develop the features, present the proposed architecture in the High level design discussions - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise -8+ years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

Responsibilities As a Logic design lead in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL Additional responsibilities: logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. Requirements:Masters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. As a Logic design lead in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL Additional responsibilities: logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. Requirements:Masters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Minimum 5+ years of experience in Chip design and development. Understand CPU / GPU / RISC V architectures. Expertise in one of the architecture and design of Core units (Fetch, Decode, arithmetic units -adders, multipliers, L1/L2/L3 cache , Mem , IO ) Understand RISC V core Experience with VLSI Design in VHDL / Verilog Preferred technical and professional experience Hiring manager and Recruiter should collaborate to create the relevant verbiage.

Responsibilities As a Logic design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLLAdditional responsibilities:logic (RTL) design, timing closure, CDC analysis etc.Understand and Design Power efficient logic.Agile project planning and execution.Requirements:Masters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Minimum 5+ years of experience in Chip design and development. Understand CPU / GPU / RISC V architectures. Expertise in one of the architecture and design of Core units (Fetch, Decode, arithmetic units -adders, multipliers, L1/L2/L3 cache , Mem , IO ) Understand RISC V core Experience with VLSI Design in VHDL / Verilog

Responsibilities As a Logic design lead in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL Additional responsibilities: logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. Requirements:Masters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Minimum 8+ years of experience in Chip design and development. Understand CPU / GPU / RISC V architectures. Expertise in one of the architecture and design of Core units (Fetch, Decode, arithmetic units -adders, multipliers, L1/L2/L3 cache , Mem , IO ) Understand RISC V core Experience with VLSI Design in VHDL / Verilog

Project Role : Application Lead Project Role Description : Lead the effort to design, build and configure applications, acting as the primary point of contact. Must have skills : Data Center Networking Technologies Operations Good to have skills : Infoblox DNS/ BloxOne & NIOS, Infoblox DDI Minimum 5 year(s) of experience is required Educational Qualification : 15 years full time education About The Role :highly skilled Network Engineer with extensive experience in Infoblox DNS, specifically BloxOne & NIOS, to join our dynamic team. This role will be instrumental in ensuring the reliability, security, and optimal performance of our organization's critical network infrastructure.Responsibilities:DNS Administration:Manage and maintain Infoblox NIOS appliances, including configuration, troubleshooting, and performance tuning.Implement and enforce DNS security best practices, such as DNSSEC, DNS Firewall, and IP Threat Defense.Design and implement DNS failover and redundancy strategies to ensure high availability.Troubleshoot DNS-related issues, including DNS resolution failures, slow DNS queries, and DNS attacks.IP Address Management (IPAM):Manage and allocate IP addresses using Infoblox IPAM.Monitor IP address utilization and plan for future growth.Implement IP address management policies and procedures.DHCP:Configure and manage DHCP services using Infoblox DHCP.Troubleshoot DHCP-related issues, such as IP address conflicts and DHCP lease failures.Network Automation:Automate routine tasks using scripting languages (e.g., Python, PowerShell) and APIs to improve efficiency and reduce human error.Develop and maintain automation scripts for DNS, DHCP, and IPAM tasks.Security:Stay up-to-date with the latest security threats and vulnerabilities related to DNS and IPAM.Implement security measures to protect the network infrastructure from attacks.Conduct regular security audits and vulnerability assessments.Troubleshooting:Diagnose and resolve complex network issues, including DNS, DHCP, and IPAM problems.Utilize network troubleshooting tools to identify and isolate network failures.Documentation:Create and maintain clear and concise documentation for network configurations, procedures, and troubleshooting steps.Qualifications:Strong understanding of DNS, DHCP, and IPAM protocols.Extensive experience with Infoblox NIOS, including BloxOne DDI.Proficiency in scripting languages (e.g., Python, PowerShell).Knowledge of network security best practices.Strong troubleshooting and problem-solving skills.Excellent communication and interpersonal skills.Ability to work independently and as part of a team.Relevant certifications (e.g. CCNA, CCNP, DDIA, DDIP ) are preferred.If you are a passionate network engineer with a strong foundation in Infoblox DNS and a desire to work on cutting-edge technologies, we encourage you to apply. Qualifications 15 years full time education

About The Role : Performs functional verification of IP logic to ensure design will meet specification requirements. Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Participates in the definition of verification infrastructure and related TFMs needed for functional design verification. Qualifications Candidate should possess a bachelor's degree in electrical, Electronics, Computer Engineering or Computer Science or any related field with 6+ years' experience-OR -a Master's degree Electrical, Electronics, Computer Engineering or Computer Science or any related field with 4+ years of experienceMandatory Skills :- SV /UVM, Mirco, test bench , test plan creation , coverage analysis , debugging/problem solving skills .Preferred skills :- BFM development , third party VIP integration , evaluation of VIP's , formal verification skills and c++ Preferred Protocol knowledge on PCIE , Cxl ,Solid verbal/written communication skills.o Effective team player with continuous learning mindset.Be willing to balance multiple tasks. Prior experience in IP development teams would be an added advantage.The candidate must be able to work independently and be self-motivated to identify, innovate upon, architect and deploy Formal Verification solutions. Experience in BFM development Inside this Business Group The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel's transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologiesspanning software, processors, storage, I/O, and networking solutionsthat fuel cloud, communications, enterprise, and government data centers around the world.

About The Role : Creates quality emulation collaterals using UVM System Verilog/SystemC and integrates it with the emulation/FPGA model. Tests and debugs the emulation/FPGA model and collaterals for validation readiness. Defines and develops new capabilities & HW/SW tools to enable acceleration of RTL and improve emulation/FPGA model usability for pre-silicon and post-silicon functional and performance validation as well as SW development/validation. Develops improvements to usability by RTL validation and debugging of failing RTL tests on the emulation platform. Interfaces with and provides guidance to presilicon Validation teams for optimizing pre-silicon validation environments, test suites and methodologies for emulation efficiency. Develops and applies automation aids, flows and scripts in support of emulation ease of use and improvement of equipment utilization. Job Experience: Technical experience in verification of RTL-based digital systems with very good understating of various system level flowsExperience leading development of verification architecture based on evolving requirement from IP/SOC customersExperience with RTL design, Verilog and simulation, debug tools such as Verdi, System Verilog/SystemC based verification techniques.Experience in debugging and isolation techniques including writing checkers, monitors, assertions and necessary DPI interfaces for co-emulation environmentsExperience in SW Programming/scripting and debug such as C, C++, Perl, PythonWork experience creating a self-checking emulation/simulation test benchHighly proficient in UVM techniques for verificationHands-on experience of emulation and simulation BFM based verificationGood understanding of architectural design documents(micro-architecture documents, integration documents)Preferably good understanding of emulation/simulation platform with major vendors (Synopsys, cadence )Protocol knowledge :PCIE, CXL, UCIe, CHI, DDR Good understanding of CPU architecture (Intel/AMD/Arm/GPU)Highly proficient with coherent, non-coherent and concurrent traffic validationExperience with emulation based systems such as Synopsys ZeBu, Cadence Palladium or Mentor Graphic VeloceExperience in building emulation based models for large scale designs is a plus Job Responsibilities: Work closely with peers in architecture, design and verification teamsShould be able to review the IP teams requirements, come up with verification plan, test plan, micro-arch, identify scenarios and design intent and develop verification strategies which can ensure defect free IP'sMaintain generic emulation based verification environment and regression setups for various IP'sLeads activities driving the development of various stimulus to support the emulation based verification of various IP'sDevelop and maintain UVM environments for IP interfacesWork in cross-functional teams to deliver bug free features in a timely manner Qualifications QualificationsThis position requires meeting the below minimum qualifications to be initially considered. Preferred qualifications are in addition to the minimum requirements and are considered a major plus.Minimum Qualifications:Must have a Bachelor's degree with 15+ year experience or Master's degree in Electronics and Computer Engineering with relevant experience of at least 10+ years Inside this Business Group In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel's products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore's Law and groundbreaking innovations. DEG is Intel's engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.