FPGA /ASIC VERIFICATION TEAM LEAD

Role Overview: You are an experienced and motivated FPGA Verification Team Lead joining the hardware engineering team. Your main responsibility will be to plan and build a UVM SV environment and lead a team of verification engineers to ensure the functional verification of a full FPGA design. Key Responsibilities: - Lead and mentor FPGA verification engineers - Plan and implement verification plans, strategies, and methodologies - Work closely with FPGA designers and system architects - Develop and maintain verification environments and agents using System Verilog UVM methodologies - Monitor and report verification progress, coverage metrics, and quality indicators - Support regression testing, bug tracking, and issue resolution during the development cycle - Track verification progress using Agile tools (e.g., Jira, Azure DevOps) and provide regular status updates and metrics Qualifications Required: - Bachelors degree in electrical engineering, Computer Engineering or Computer Science - 10+ years of experience in FPGA or ASIC verification, with at least 2 years in a leadership or team lead role - Strong hands-on experience in writing System-verilog UVM agents and full UVM environments from scratch - Strong hands-on experience in writing verification plans and coverage plans - Solid understanding of FPGA architecture and RTL design - Familiarity with version control systems (e.g., Git) and issue tracking tools (e.g., Jira) - Excellent leadership, communication, and organizational skills - Strong experience with simulation tools such as Xcelium, Questasim or VCS - Strong debug capabilities Additional Details: Omit this section as no additional details of the company are present in the job description.,