Custom Design Static Timing Analysis Engineer, Silicon Google

2.0 - 6.0 years

0 Lacs

karnataka

On-site

The ideal candidate for this role should possess a Bachelor's degree or equivalent practical experience along with a minimum of 2 years of experience in developing and maintaining STA constraints and scripts. It is essential to have prior experience working collaboratively in a team of DFT engineers, specifically with Register-Transfer Level (RTL) and Physical Designer Engineers. Preferred qualifications for this position include a Bachelor's or Master's degree in Electrical Engineering or Computer Science, or relevant practical experience. The candidate should have at least 6 years of experience in Static Timing Analysis with exposure to mixed signal design. Proficiency in flow methodology and development is highly desirable, as well as experience in coding using perl, python, and tcl scripting languages. Strong problem-solving and decision-making skills are essential for this role. As part of this role, you will be joining a diverse team dedicated to pushing boundaries and developing custom silicon solutions that drive Google's direct-to-consumer products into the future. Your contributions will be instrumental in shaping the innovation behind products that are beloved by millions globally, with a focus on delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. As a member of our team, you will have the opportunity to leverage the best of Google AI, Software, and Hardware to create revolutionary experiences that are profoundly helpful. Our work involves researching, designing, and developing new technologies and hardware to accelerate computing, ensuring that it is faster, seamless, and more powerful, ultimately aiming to enhance people's lives through innovative technology. Key Responsibilities: - Develop and maintain Static Timing Analysis (STA) and flow methodologies. - Create flow for custom/Analog and Mixed Signal (AMS) IP collateral, encompassing all view generation and QA checks. - Ensure timing closure for Place and Route (PnR) blocks. - Validate time constraint development. In this role, your expertise and contributions will play a crucial role in advancing the next generation of hardware experiences, contributing to a future where technology enhances and enriches the lives of individuals worldwide.,

Posted 1 week ago

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