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Custom Design Static Timing Analysis Engineer, Silicon Google

2.0 - 6.0 years

0 Lacs

karnataka

On-site

The ideal candidate for this role should possess a Bachelor's degree or equivalent practical experience along with a minimum of 2 years of experience in developing and maintaining STA constraints and scripts. It is essential to have prior experience working collaboratively in a team of DFT engineers, specifically with Register-Transfer Level (RTL) and Physical Designer Engineers. Preferred qualifications for this position include a Bachelor's or Master's degree in Electrical Engineering or Computer Science, or relevant practical experience. The candidate should have at least 6 years of experience in Static Timing Analysis with exposure to mixed signal design. Proficiency in flow methodology ...

Posted 1 month ago

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