Senior RTL Design Engineer DSP/ASIC/FPGA Talenton Technology Services

8.0 - 13.0 years

40 - 80 Lacs

bengaluru

Work from Office

Senior RTL Design Engineer DSP / ASIC / FPGA Experience: 10 to 15 years Location: Bangalore (On-site) Employment Type: Full-time / Permanent About the Role We are seeking a highly skilled Senior RTL Design Engineer to join our digital design team. The selected candidate will be responsible for the RTL design and development of signal processing pipelines for high-performance ASIC and FPGA-based SoCs. Key Responsibilities Develop and integrate custom sub-components of the digital signal processing pipeline such as filters, FFTs, control logic, etc. Write micro-architecture specifications, code RTL, and perform verification and validation of DSP components. Optimize RTL for performance, area, ...

Posted 2 weeks ago

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RTL - Tech Lead CoreEL Technologies

7.0 - 11.0 years

0 Lacs

karnataka

On-site

Role Overview: As a Tech Lead at the company, you will be responsible for defining DSP, System, and Board architecture, creating proposals for new project inquiries, and effectively managing the team. Your role will involve partitioning algorithms for implementation in FPGA and/or software, identifying building blocks and Signal Processing functions, and providing estimates on FPGA resources, computation bandwidth, and memory bandwidth. Additionally, you will create module level details, maintain project documentation, provide customer support during integration phases, and contribute to design, verification, and validation methodologies. Key Responsibilities: - Define DSP, System, and Board...

Posted 3 weeks ago

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Technical Lead (FPGA Developer) HyrEzy Talent Solutions LLP

5.0 - 9.0 years

0 Lacs

haryana

On-site

You should have experience working with USRP N310/X310 (N3xx/X3x0) and possess a deep understanding of FPGA Architecture. Additionally, you must be proficient in writing your own RTL custom HDL or integrating IP components, including VHDL, Verilog, System Verilog, Vivado HLS, Xilinx IP, and Vivado Block Diagram. It is essential that you have developed RFNoC Blocks and have a good grasp of the USRP Hardware Driver (UHD). Your responsibilities will include creating custom FPGA logic in RFNoC Blocks, utilizing existing RFNoC Blocks library, and understanding the GNU Radio interface to RFNoC Block. Furthermore, you will be involved in FPGA debugging, hardware/software integration, and implementi...

Posted 3 months ago

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FPGA Developer Bonzer Business Solutions Pvt Ltd.

7.0 - 9.0 years

2 - 6 Lacs

New Delhi, Bengaluru

Work from Office

Skills required: 1. Should have worked on USRP N310/X310 (N3xx/X3x0) 2. In-depth Knowledge of FPGA Architecture 3. Able to write own RTL custom HDL or drops in IP a) VHDL, Verilog, System,Verilog, Vivado HLS b) Xilinx IP, Vivado Block Diagram 4. Should have developed RFNoC Block 5. Have working knowledge of USRP Hardware Driver (UHD) 6. Able to write custom FPGA logic in RFNoC Blocks 7. Able to use library of existing RFNoC Blocks a) FFT, FIR, Signal Generator, Fosphor 8. Have understanding of GNU Radio interface to RFNoC Block 9. FPGA debugging and HW/SW integration 10. Thorough understanding of appropriate coding styles for FPGAs, and trade-offs for density and speed 11. In-depth knowledge...

Posted 3 months ago

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Software Defined Radio (SDR) Developer Topgear Consultants

3.0 - 8.0 years

8 - 12 Lacs

Hyderabad

Work from Office

Job Description This is an urgent requirementimmediate availability is highly desirable Job Title: Software Defined Radio (SDR) Developer Industry: Electronics / Telecommunications Location: Hyderabad, India Qualification: B.Tech / M.Tech (preferred) Experience: 310 years (flexible based on skills) Job Description: We are looking for a Software Defined Radio (SDR) Developer with strong expertise in wireless communication and digital signal processing. The ideal candidate will have hands-on experience in SDR implementation on FPGA/SoC platforms and be passionate about working on cutting-edge communication technologies. Key Responsibilities: Implement and optimize channel encoding/decoding tec...

Posted 4 months ago

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