95 Finfet Jobs - Page 4

You're an experienced and passionate Analog and Mixed-Signal (A&MS) Senior Circuit Design Expert with a strong background in PLL and SERDES design . You bring a deep understanding of mixed-signal techniques for dynamic and static power reduction, performance enhancement, and area reduction. Your expertise covers circuit architectures simulation, circuit layout, and knowledge of bipolar, CMOS, passive structures, and interconnect failure modes in advanced FinFET technology nodes. You excel at developing Analog Full Custom circuit macros , including PLLs, Clock Path Functions, clocking solutions, TX/RX datapaths, and power management and regulation for High Speed PHY IP in both planar and FinF...

About the Role: We are seeking a highly skilled and experienced Analog Layout Manager to lead our layout engineering team in the development of cutting-edge analog and mixed-signal ICs. This role requires deep technical expertise in analog layout, strong leadership capabilities, and the ability to deliver high-quality silicon in aggressive timelines. Key Responsibilities: Lead and manage a team of analog layout engineers to deliver high-quality layouts for analog and mixed-signal IPs (e.g., ADCs, DACs, PLLs, LDOs, PMICs, etc.) Own the floor planning, partitioning, and layout strategy for complex blocks and full chip integration. Collaborate closely with circuit design, verification, and phys...

• Drive Area estimation, Floor Planning, Placement, Routing, Power planning, Verification, EMIR, ESD-LUP Verification & Tape out. • Understanding of low parasitic, high frequency design techniques. • Finfet process & Lower nodes; 2nm/3nm/5nm/7nm Required Candidate profile • Exp with Cadence (Virtuoso), Synopsys (CC), Calibre & ICV verification tools like LVS, DRC, Extraction. • Debugging/fixing LVS/DRC errors • Experience with EMIR, PERC tools. • Skill/TCL scripting.

Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues. Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineer...

Requirement : Analog Circuit Design Lead Experience Range : 7 - 12 Yrs. Work Location(s) : Bengaluru, Karnataka Candidates who are ready to join Immediately Requirements: Experience in entire Analog IP development including circuit design, layout, AMS verification, and characterization. Must have led the entire Analog IP development cycle and team. Circuit Design implementation of IPs including LDOs, Band Gap reference, Current Generators, POR, ADC/DACs, PLLs, Oscillators, General Purpose IOs, Temperature sensor, SERDES, PHYs, Die to Die interconnect, High-speed IOs, etc. Analog/custom layout design in advanced CMOS process. Ability to understand design constraints and implement high-quality...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Overview In this highly cross functional role, you will be part of the Global Design Enablement team responsible for various aspects of PDK development across Custom, Analog and RF technology nodes. As a member of the CAD team, you will be working closely with Custom, Analog & RF Engineering design community to develop & support customized tools and flows for Schematic & Layout design, Circuit Simulation, IP characterization, Custom/Analog P&R and transistor-level EM/IR flows. You will also have the responsibility to collaborate with our Foundry and EDA partners to deploy best-in class EDA tools and fl...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: In this highly cross functional role, you will be part of the Global Design Enablement team responsible for various aspects of PDK development across Custom, Analog and RF technology nodes. As a member of the CAD team, you will be working closely with Custom, Analog & RF Engineering design community to develop & support customized tools and flows for Schematic & Layout design, Circuit Simulation, IP characterization, Custom/Analog P&R and transistor-level EM/IR flows. You will also have the responsibility to collaborate with our Foundry and EDA partners to deploy best-in class EDA tools and flows in additi...

What are we seeking- Our Technology Solutions Sales organization (TSS) hoping you as a dynamic technical professional would be a great fit as an Applications Engineering Manager (AEM) leading a growing team of dedicated field applications engineers in Siemens EDA's Bangalore office. This is both a deep leadership role and one that requires business approach, a strategic understanding of the market, and a flexible approach to tactical field execution. You will also need to remain highly organized in a constantly evolving environment, balance multiple considerations in quick decision-making and prioritization situations, and manage professional relationships inside and outside the organization...

Experience Required: 8+ years to 10+ Education: Btech/Mtech Electronics/Electrical engineering Skills/Experience: Experience in Analog Mixed-signal DDR/HBM IP layout and verification of high-speed digital layout and solid understanding of high speed signal Experience in managing the technical aspects of project execution, ensuring timely delivery maintaining high quality standards, Advanced understanding of Deep submicron effects and mitigation, Advanced tool usage, Advanced floorplanning techniques, understand digital flow, Advanced strategies, Solid understanding of CMOS and FinFET layouts and process technology in 28nm and smaller, Good understanding of ESD and latchup layout design consi...

Alternate Job Titles: Senior Layout Design Engineer Analog Mixed-Signal Layout Engineer Staff Engineer, Layout Design We Are: At Synopsys, we drive the innovations that shape the way we live and connect Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: You are a seasoned professional with over 6 years of experience in Analog Mixed-Signal layout and verification You possess a robust understanding of deep submicron ef...

Experience in memory layout. Memory Leafcell layout library design from scratch, including top-level integration. Knowledge of different types of memory architectures. Proficient in DRC, LVS, ERC, boundary conditions. Contact at Shubhanshi@incise.in Required Candidate profile 3-8 years of experience in Memory/Custom Layout design. Cadence Virtuoso layout editor and Calibre physical verification flow

Layout concepts: Good knowledge in layout matching techniques and it usage Able to do floorplan, placement , routing and lvs-drc clean at block level Hands on experience in OPAMP , LDO, BGA and reference generate blocks Handle the block independently and able to communicate with design team Expertise in EM and IR fixes Good knowledge in floor planning of IPs like RX, TX and Synth IPs Understanding of DRC errors and fixing it including density errors . Good knowledge in Tsmc 6nm technology node Interested candidates can share their resumes to shubhanshi@incise.in

Role & responsibilities 1.Job description - Analog Layout: Exciting Opportunity for Analog Layout Engineers ! Elevate your career with Digicomm Semiconductor Private Limited and take the next leap in your professional journey. Join us for unparalleled growth and development. Responsibilities:- Excellent work experience in Analog / Mixed Signal Layout design in advanced FinFET processes like 16nm, 12nm, 10nm, 7nm, 5nm, 3nm Expertise on complete PNR flow CTS,routing, Timing Closure. Hands on experience in any or multiple critical blocks such as SERDES, PHY, HDMI, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc. Excellent underst...

• Physical Design of blocks & handle Complex block implementation. • Floorplan optimization for area, Power & Timing. • Block-level PnR & close Design to meet Timing, area & Power constraints. • Implement ECOs to fix timing, noise & EM-IR violations. Required Candidate profile * Exp in RTL Synthesis for PnR using small geometry FinFET. * Strong in Physical Design incl. physically aware Synthesis, floor-planning, PnR * Logic equivalency RTL2Synthesis & Synthesis2APR netlist.

Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues. Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineer...

Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues. Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineer...

Dear Analog Layout Engineers, We, Cyient Semiconductor is hiring for Sr/ Staff Analog Layout Engineers: 7nm/ Lesser with DDR Exp for Offshore-Onshore Model based Global Product Solution from Scratch. Exp Range: 5-8 Yrs Pls Note: Only Looking for Immediate Joiners or within 15-20 days NP, who can work on Global Product Solution from Scratch About the Role We are seeking a highly skilled Analog Mixed-Signal (AMS) Layout Engineer with proven expertise in 7nm or smaller technology nodes , FinFET architecture , and DDR interface layouts . The ideal candidate will work closely with design teams to deliver high-performance, low-power, and area-efficient layouts for cutting-edge semiconductor produc...

Dear Analog Layout Engineers, We, Cyient Semiconductor is hiring for Sr Analog Layout Engineers: High Speed: 7nm/ Lesser Exp for Offshore-Onshore Model based Global Product Solution from Scratch. Exp Range: 3-5 Yrs Pls Note: Only Looking for Immediate Joiners or within 15-20 days NP, who can work on Global Product Solution from Scratch About the Role We are seeking an Analog Mixed-Signal (AMS) Layout Engineer with deep expertise in 7nm or smaller process nodes , FinFET technologies , and high-speed layout design . The ideal candidate will have hands-on experience in complex analog, digital, and mixed-signal layouts, ensuring optimal performance, power, and area for cutting-edge semiconductor...

: To work independently on block/IP levels analog layout design from schematic. Estimating the Area, Optimizing Floorplan, Routing and Verifications. Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 5,7,10, 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence Virtuoso Editor & Calibre RVE Good interpersonal skills and critical thinking abilities to resolve the issue technically, and professionally. Key Responsibilities: Independently execute block/IP-level analog layout from schematics, including area estimation, floorplan optimization, routing, a...

: To work independently on block/IP levels analog layout design from schematic. Estimating the Area, Optimizing Floorplan, Routing and Verifications. Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 5,7,10, 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence Virtuoso Editor & Calibre RVE Good interpersonal skills and critical thinking abilities to resolve the issue technically, and professionally. Key Responsibilities: Independently execute block/IP-level analog layout from schematics, including area estimation, floorplan optimization, routing, a...