61 Finfet Jobs - Page 3

Alternate Job Titles: Senior Layout Design Engineer Analog Mixed-Signal Layout Engineer Staff Engineer, Layout Design We Are: At Synopsys, we drive the innovations that shape the way we live and connect Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: You are a seasoned professional with over 6 years of experience in Analog Mixed-Signal layout and verification You possess a robust understanding of deep submicron effects and mitigation, advanced tool usage, floor-planning, and routing Your expertise extends to CMOS and FinFET layouts and process technology in 28nm and below You are familiar with the layout design flow, including top-level verification flow, DRC/LVS, LPE, and have a good grasp of basic ESD and latch-up layout design considerations You understand power routes, EM and IR considerations, and DFM You have exposure to Analog/Mixed Signal circuit layout (e-g , RX, TX, PLL) Your excellent written and verbal communication skills enable you to interact effectively with internal development teams You are passionate about technology and thrive in a collaborative environment where your skills contribute to groundbreaking innovations, What Youll Be Doing: Designing and verifying complex Analog Mixed-Signal layouts, ensuring high-quality and reliable IPs, Collaborating with cross-functional teams to optimize layout designs for performance and manufacturability, Utilizing advanced tools and methodologies to mitigate deep submicron effects, Conducting floor-planning, routing, and top-level verification, Ensuring compliance with DRC, LVS, LPE standards and addressing ESD and latch-up considerations, Optimizing power routes and addressing EM and IR considerations for robust designs, The Impact You Will Have: Enhancing the performance and reliability of our high-speed SerDes IPs and other critical components, Driving innovation in Analog Mixed-Signal layout design, contributing to cutting-edge technology developments, Ensuring seamless integration and functionality of our IPs in diverse applications, Improving design efficiency and manufacturability through advanced layout techniques, Contributing to the success of our product development lifecycle by delivering high-quality designs, Supporting our mission to lead in chip design and IP integration, shaping the future of technology, What Youll Need: 6+ years of experience in Analog Mixed-Signal layout and verification, Advanced understanding of deep submicron effects and mitigation techniques, Proficiency in using advanced layout design tools and methodologies, Solid understanding of CMOS and FinFET layouts and process technology in 28nm and below, Familiarity with layout design flow, including top-level verification flow, DRC/LVS, LPE, Who You Are: You are detail-oriented, methodical, and have a deep understanding of layout design principles Your ability to communicate effectively and work collaboratively with cross-functional teams is exceptional You are proactive, always looking for innovative solutions to complex problems, and your passion for technology drives you to stay updated with the latest industry trends and advancements, The Team Youll Be A Part Of: You will be part of a dynamic and innovative team focused on developing high-performance Analog Mixed-Signal layouts Our team collaborates closely with other engineering departments to ensure the seamless integration and functionality of our IPs We value creativity, continuous learning, and a collaborative spirit to push the boundaries of technology and innovation, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process,

Experience in memory layout. Memory Leafcell layout library design from scratch, including top-level integration. Knowledge of different types of memory architectures. Proficient in DRC, LVS, ERC, boundary conditions. Contact at Shubhanshi@incise.in Required Candidate profile 3-8 years of experience in Memory/Custom Layout design. Cadence Virtuoso layout editor and Calibre physical verification flow

Layout concepts: Good knowledge in layout matching techniques and it usage Able to do floorplan, placement , routing and lvs-drc clean at block level Hands on experience in OPAMP , LDO, BGA and reference generate blocks Handle the block independently and able to communicate with design team Expertise in EM and IR fixes Good knowledge in floor planning of IPs like RX, TX and Synth IPs Understanding of DRC errors and fixing it including density errors . Good knowledge in Tsmc 6nm technology node Interested candidates can share their resumes to shubhanshi@incise.in

Role & responsibilities 1.Job description - Analog Layout: Exciting Opportunity for Analog Layout Engineers ! Elevate your career with Digicomm Semiconductor Private Limited and take the next leap in your professional journey. Join us for unparalleled growth and development. Responsibilities:- Excellent work experience in Analog / Mixed Signal Layout design in advanced FinFET processes like 16nm, 12nm, 10nm, 7nm, 5nm, 3nm Expertise on complete PNR flow CTS,routing, Timing Closure. Hands on experience in any or multiple critical blocks such as SERDES, PHY, HDMI, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc. Excellent understanding of CMOS / Bi-CMOS / SOI / FinFET process Excellent understanding of CMOS / Bi-CMOS / SOI / FinFET process Experience in AMS IP integration in full chip according to the guidelines demanded by the Full Chip needs Excellent problem-solving skills in Routing Congestion, Physical Verification in Custom Layout Qualifications:- BTECH/MTECH Location: Bangalore & Noida Experience:- The Engineers with 5 to 10 years of Experience 2.Job description - Physical Verification- Exciting Opportunity for Physical Verification Engineers ! Elevate your career with Digicomm Semiconductor Private Limited and take the next leap in your professional journey. Join us for unparalleled growth and development. Responsibilities:- Design Rule Checking (DRC): Run DRC checks using industry-standard tools to identify violations of manufacturing design rules. Collaborate with layout designers to resolve DRC issues. Layout vs. Schematic (LVS) Verification: Perform LVS checks to ensure that the physical layout accurately matches the schematic and that there are no electrical connectivity discrepancies. Electrical Rule Checking (ERC): Verify that the layout adheres to electrical constraints and requirements, such as voltage and current limitations, ensuring that the IC functions as intended. Design for Manufacturing (DFM): Collaborate with design and manufacturing teams to optimize the layout for the semiconductor fabrication process. Address lithography and process variation concerns. Process Technology Calibration: Calibrate layout extraction tools and parameters to match the specific process technology used for fabrication. Resolution Enhancement Techniques (RET): Implement RET techniques to improve the printability of layout patterns during the photolithography process. Fill Insertion: Insert fill cells into the layout to improve planarity and reduce manufacturing-related issues, such as wafer warping and stress. Multi-Patterning and Advanced Nodes: Deal with challenges specific to advanced process nodes, including multi-patterning, coloring, and metal stack variations. Hotspot Analysis: Identify and address potential hotspot areas that may lead to manufacturing defects or yield issues. Post-Processing Simulation: Perform post-processing simulations to verify that the layout is compatible with the manufacturing process and does not introduce unwanted parasitics. Process Integration Checks: Collaborate with process integration teams to ensure the smooth integration of the design with the semiconductor fabrication process. Documentation: Maintain detailed documentation of verification processes, methodologies, and results. Qualifications:- BTECH/MTECH Experience:- The Engineers with 5 to 10 years of Experience Location:- Bangalore/ Noida

• Physical Design of blocks & handle Complex block implementation. • Floorplan optimization for area, Power & Timing. • Block-level PnR & close Design to meet Timing, area & Power constraints. • Implement ECOs to fix timing, noise & EM-IR violations. Required Candidate profile * Exp in RTL Synthesis for PnR using small geometry FinFET. * Strong in Physical Design incl. physically aware Synthesis, floor-planning, PnR * Logic equivalency RTL2Synthesis & Synthesis2APR netlist.

Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues. Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 2+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 4+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR High School diploma or equivalent and 6+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. 2+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap). 2-5 years of experience in Custom layout and Memory Layout design. Memory Leafcell layout library design from scratch including top level integration. Good knowledge on different types of memory architectures and compilers Good knowledge in optimized layout design for better performance. Sound knowledge & hands on experience in Finfet technology, DRC limitations and work closely with CAD engineers for better customization of DRC and tiling layout. Proficient in physical verification flow & debug, like DRC, LVS, ERC, Boundary conditions. Proficient in Cadence Virtuoso layout editor and Calibre physical verification flow Proficient in SKILL and PERL for custom tiling and automations

Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues. Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 2+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 4+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. OR High School diploma or equivalent and 6+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience. 2+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap). 2-5 years of experience in Custom layout and Memory Layout design. Memory Leafcell layout library design from scratch including top level integration. Good knowledge on different types of memory architectures and compilers Good knowledge in optimized layout design for better performance. Sound knowledge & hands on experience in Finfet technology, DRC limitations and work closely with CAD engineers for better customization of DRC and tiling layout. Proficient in physical verification flow & debug, like DRC, LVS, ERC, Boundary conditions. Proficient in Cadence Virtuoso layout editor and Calibre physical verification flow Proficient in SKILL and PERL for custom tiling and automations

Dear Analog Layout Engineers, We, Cyient Semiconductor is hiring for Sr/ Staff Analog Layout Engineers: 7nm/ Lesser with DDR Exp for Offshore-Onshore Model based Global Product Solution from Scratch. Exp Range: 5-8 Yrs Pls Note: Only Looking for Immediate Joiners or within 15-20 days NP, who can work on Global Product Solution from Scratch About the Role We are seeking a highly skilled Analog Mixed-Signal (AMS) Layout Engineer with proven expertise in 7nm or smaller technology nodes , FinFET architecture , and DDR interface layouts . The ideal candidate will work closely with design teams to deliver high-performance, low-power, and area-efficient layouts for cutting-edge semiconductor products. Key Responsibilities Design and develop full-custom AMS layouts for high-speed and low-power circuits in 7nm or below process nodes . Perform layout design for FinFET devices , ensuring optimal device matching, symmetry, and parasitic control. Implement layout for DDR interfaces (DDR3/DDR4/LPDDR/DDR5) including IOs, PHY blocks, and termination circuits. Conduct layout verification (DRC/LVS/ERC/ANT checks) using industry-standard EDA tools. Collaborate with circuit designers to meet performance, power, and area (PPA) targets. Optimize layouts for signal integrity, IR drop, electromigration , and manufacturability. Participate in design reviews and provide feedback on floorplanning, routing strategies , and parasitic extraction (PEX) results. Ensure compliance with foundry process design kits (PDK) and fabrication guidelines. Required Skills & Qualifications Bachelors or Master’s degree in Electronics, Electrical Engineering, or VLSI Design. 5-8 years of experience in AMS layout engineering. Hands-on experience with 7nm, 5nm, or advanced FinFET nodes in high-volume production. Strong knowledge of DDR interface layouts and signal integrity considerations. Proficiency in Cadence Virtuoso, Mentor Calibre, Synopsys IC Validator , or equivalent tools. Deep understanding of layout techniques for analog, digital, and mixed-signal blocks (e.g., PLLs, SerDes, ADC/DAC, IOs). Experience with power distribution, shielding, and ESD structures . Excellent problem-solving skills.

Dear Analog Layout Engineers, We, Cyient Semiconductor is hiring for Sr Analog Layout Engineers: High Speed: 7nm/ Lesser Exp for Offshore-Onshore Model based Global Product Solution from Scratch. Exp Range: 3-5 Yrs Pls Note: Only Looking for Immediate Joiners or within 15-20 days NP, who can work on Global Product Solution from Scratch About the Role We are seeking an Analog Mixed-Signal (AMS) Layout Engineer with deep expertise in 7nm or smaller process nodes , FinFET technologies , and high-speed layout design . The ideal candidate will have hands-on experience in complex analog, digital, and mixed-signal layouts, ensuring optimal performance, power, and area for cutting-edge semiconductor products. Key Responsibilities Perform full-custom Analog layout design for AMS circuits in advanced nodes (7nm or below). Work on FinFET device layouts , ensuring compliance with foundry-specific DRC/LVS requirements. Design high-speed analog/mixed-signal blocks such as SerDes, PLL, ADC/DAC, LDO, and other high-performance IPs. Collaborate with circuit designers to understand schematic intent and translate it into optimized physical layouts. Execute layout parasitic extraction (PEX) and work closely with verification teams for post-layout simulations. Ensure electromigration (EM), IR drop, and signal integrity compliance in layouts. Follow design-for-manufacturability (DFM) guidelines to maximize yield. Debug and resolve LVS/DRC violations in advanced technology nodes. Required Skills & Qualifications Bachelors/Masters in Electronics, VLSI, or related field . 3+ years of relevant AMS layout experience (7nm or smaller preferred). Proven expertise in FinFET layout design . Experience with high-speed analog/mixed-signal IPs (SerDes, PLLs, ADC/DAC, PHYs). Strong knowledge of Cadence Virtuoso, Calibre, Assura , or equivalent tools. Familiarity with PEX, LVS, DRC, ERC verification flows. Solid understanding of layout-dependent effects (LDEs) in advanced nodes. Strong collaboration skills with designers and verification engineers.

: To work independently on block/IP levels analog layout design from schematic. Estimating the Area, Optimizing Floorplan, Routing and Verifications. Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 5,7,10, 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence Virtuoso Editor & Calibre RVE Good interpersonal skills and critical thinking abilities to resolve the issue technically, and professionally. Key Responsibilities: Independently execute block/IP-level analog layout from schematics, including area estimation, floorplan optimization, routing, and layout verification. Perform LVS (Layout vs. Schematic) and DRC (Design Rule Check) debugging for advanced FinFET technology nodes (5nm, 7nm, 10nm, 14nm and below). Ensure layout quality by applying principles of matching, electromigration (EM), electrostatic discharge (ESD), latch-up prevention, shielding, parasitic management, and short channel effects. Utilize industry-standard EDA tools such as Cadence Virtuoso Editor and Calibre RVE for layout and verification tasks. Primary Skills : Analog Layout Design(Block/IP level) LVS/DRC Debugging FinFET Technology Node Experience(5nm, 7nm, 10nm, 14nm and below) EDA Tools Cadence Virtuoso Editor Calibre RVE Layout Optimization Area estimation Floorplanning Routing Secondary Skills : These support the primary responsibilities and enhance performance: Understanding of Physical Design Concepts: Matching Electromigration (EM) Electrostatic Discharge (ESD) Latch-Up Shielding Parasitics Short Channel Effects Critical Thinking & Problem Solving Interpersonal and Communication Skills Team Collaboration Educational Qualification: Bachelor's or Master's Degree.

: To work independently on block/IP levels analog layout design from schematic. Estimating the Area, Optimizing Floorplan, Routing and Verifications. Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 5,7,10, 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence Virtuoso Editor & Calibre RVE Good interpersonal skills and critical thinking abilities to resolve the issue technically, and professionally. Key Responsibilities: Independently execute block/IP-level analog layout from schematics, including area estimation, floorplan optimization, routing, and layout verification. Perform LVS (Layout vs. Schematic) and DRC (Design Rule Check) debugging for advanced FinFET technology nodes (5nm, 7nm, 10nm, 14nm and below). Ensure layout quality by applying principles of matching, electromigration (EM), electrostatic discharge (ESD), latch-up prevention, shielding, parasitic management, and short channel effects. Utilize industry-standard EDA tools such as Cadence Virtuoso Editor and Calibre RVE for layout and verification tasks. Primary Skills : Analog Layout Design(Block/IP level) LVS/DRC Debugging FinFET Technology Node Experience(5nm, 7nm, 10nm, 14nm and below) EDA Tools Cadence Virtuoso Editor Calibre RVE Layout Optimization Area estimation Floorplanning Routing Secondary Skills : These support the primary responsibilities and enhance performance: Understanding of Physical Design Concepts: Matching Electromigration (EM) Electrostatic Discharge (ESD) Latch-Up Shielding Parasitics Short Channel Effects Critical Thinking & Problem Solving Interpersonal and Communication Skills Team Collaboration Educational Qualification: Bachelor"s or Master"s Degree.