95 Finfet Jobs - Page 2

Position: Analog Design Engineer Experience: 2 - 7 Years Location: Bangalore / Hyderabad Key Skills & Experience Required: Strong expertise in Power Management Circuits DC-DC Converters, LDOs, etc. Hands-on experience in High Voltage Power Management BCD, GaN-related process exposure. Proficiency in High-Speed SERDES Design or Sub-blocks (FinFET experience is a strong plus). Strong problem-solving skills and a passion for innovation in semiconductor design. If you are passionate about pushing the boundaries of semiconductor design, we would love to hear from you!

Roles and Responsibilities Design analog layouts using Cadence Virtuoso for FinFET devices with PLL and SerDes interfaces. Perform DRC, LVS, and mixed signal simulations to ensure design integrity. Collaborate with cross-functional teams to resolve design issues and optimize designs. Develop expertise in Caliber technology for high-speed I/O applications. Ensure compliance with industry standards and company guidelines.

Responsibilities Perform full-custom analog layout for advanced nodes (28nm and below ,TSMC,FinFET/CMOS technologies) .Work on block-level and top-level layouts of circuits such as: PLLs, ADCs, DACs, LDOs, Bandgaps, High-speed IOs, SerDes, RF blocks

Semiconductor Device Physicist Job Title: Semiconductor Device Physicist Location: [Corporate R&D / Process Development Labs] Experience: 3-10 years Education: Ph.D. in Semiconductor Physics, Electronics, or Materials Science Responsibilities: Model and analyze semiconductor devices (FinFET, GAA, TFET, etc.) at nanometer nodes Support process and device teams with TCAD simulations (Synopsys Sentaurus, Silvaco) Investigate novel device structures for performance and reliability Generate physical models for use in EDA/PDK development Requirements: Strong understanding of semiconductor physics and advanced CMOS/More-than-Moore technologies Experience with TCAD tools and device measurement techn...

Years: 3yrs to 8yrs Location: Bangalore JD: 3-8 years of experience in Memory/Custom Layout design. Memory Leafcell layout library design from scratch including top level integration. Good knowledge on different types of memory architectures. Good knowledge in optimized layout design for better performance. Sound knowledge & hands on experience in Finfet technology, layout design and DRC limitations. Proficient in physical verification flow & debug, like DRC, LVS, ERC, Boundary conditions. Good Knowledge in EM and IR run and fix. Proficient in Cadence Virtuoso layout editor and Calibre physical verification flow Please share updated resume to madhuri.a.sivaraju@capgemini.com

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engine...

General Summary: Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods. Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues. Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, El...

We are looking for an experienced Analog Layout Engineer with 8+ years of hands-on experience in full custom layout of analog and mixed-signal blocks. The ideal candidate should have expertise in advanced CMOS technologies and be capable of delivering high-quality layout from specifications to tape-out. Key Responsibilities: Execute full custom layout for analog/mixed-signal blocks (OpAmps, Bandgaps, LDOs, ADCs, etc.) Floorplanning, device matching, parasitic optimization, and electromigration compliance Perform DRC/LVS/ERC checks and work closely with verification teams Collaborate with circuit designers to optimize performance and area Ensure quality layout delivery in accordance with tape...

Hands-on technical, finfet expertise (nodes 12nm or below) and manage a team of 5+ members. Proven track record of managing a team of >5 members. Experience within the service industry. Performs layout and takes corrective actions in such a way that the final result meets all requirements as stated in the Design document, section layout, including all remarks from review, the customer and back annotation. Performs layout in such a way that the final result meets all general layout guidelines and matches 1-to-1 with parameter devices and hierarchy used in simulations. Create floorplan Performs DRC and takes corrective actions if needed until DRC is error free Performs LVS and takes corrective...

JD: Analog Layout, TSMC, Intel, Samsung Foundries Nodes - Finfet like 2nm, 3nm, 5nm, 7 nm Location - HYD interested candidate, Kindly share with me your updated profile to anand.arumugam@modernchipsolutions.com Or call me 9900927620 for Discussion

About The Role : To work independently on block/IP levels analog layout design from schematic. Estimating the Area, Optimizing Floorplan, Routing and Verifications. Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 5,7,10, 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence Virtuoso Editor & Calibre RVE Good interpersonal skills and critical thinking abilities to resolve the issue technically, and professionally. Key Responsibilities: Independently execute block/IP-level analog layout from schematics, including area estimation, floorplan optimizat...

Job Area :Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performanc...

Hands-on technical, finfet expertise (nodes 12nm or below) and manage a team of 5+ members. Proven track record of managing a team of >5 members. Experience within the service industry. Performs layout and takes corrective actions in such a way that the final result meets all requirements as stated in the Design document, section layout, including all remarks from review, the customer and back annotation. Performs layout in such a way that the final result meets all general layout guidelines and matches 1-to-1 with parameter devices and hierarchy used in simulations. Create floorplan Performs DRC and takes corrective actions if needed until DRC is error free Performs LVS and takes corrective...

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer ...

General Summary: Posting Title: Analog/Mixed Signal PLL Analog Designers Bangalore (BDC), India Job Function Qualcomm Mixed-Signal IP team is actively seeking for analog circuit designers (3-10yrs) to join our growing team in Bangalore, India (BDC). You will be directly involved in delivering analog and mixed-signal integrated circuits for high-speed PLL/DLL/LDO IP for SoC and the integration into Qualcomm's Mobile, Auto, IoT & Compute SoC products in leading-nodes - finfets & beyond. Design goals include low-power & low voltage analog designs to address Qualcomm's low-power wireless products. Responsibilities Hands-on experience - Analog circuit design Architecture, design, and development ...

Key Responsibilities: Perform custom layout design of high-performance and low-power memory blocks (SRAM, ROM, Register Files, CAM, etc.). Work on floorplanning, transistor-level layout, device matching, and parasitic optimization. Ensure DRC/LVS clean layouts with adherence to foundry design rules. Collaborate with circuit design teams to achieve optimal PPA (Performance, Power, Area). Conduct parasitic extraction, EM/IR analysis, and reliability checks for memory layouts. Deliver high-quality layouts meeting project deadlines and silicon success. Required Skills: Strong expertise in memory layout (SRAM, ROM, CAM, Register Files). Hands-on experience with Cadence Virtuoso, Mentor Calibre, S...

8+ years of experience in Memory/Custom Layout design. Memory Leafcell layout library design from scratch Knowledge on different types of memory architectures. Knowledge in optimized layout design for better performance. Knowledge & hands on experience in Finfet technology, layout design and DRC limitations. Proficient in physical verification flow & debug Proficient in Cadence Virtuoso layout editor and Calibre Interested can contact me at shubhanshi@incise.in

You will be responsible for memory layout design, including important memory building blocks such as control, sense amplifiers, I/O Blocks, bit cell array, and decoders in the compiler context. Your hands-on experience should include working with 16nm/14nm/10nm/7nm/Finfet process technologies. You will be expected to have expertise in top-level memory integration, DRC, LVS, density verification, and cleaning physicals across the compiler space. It is essential to have a good understanding of IR/EM related issues in memory layouts and experience with Cadence tools for layout design and Cadence/Mentor/Synopsys tools for physical verification checks. A strong knowledge of ultra-deep sub-micron ...

As an Analog Layout Design Engineer at Synopsys, you will play a pivotal role in developing cutting-edge layouts for next-generation DDR/HBM/UCIe IPs. Your primary responsibilities will include creating floorplans, routing, and conducting physical verifications to ensure high-quality deliverables that meet stringent quality standards within specified timelines. You will collaborate closely with design engineers to optimize layouts for performance, power efficiency, and area utilization. By implementing layout matching techniques, ESD, latch-up, EMIR, DFM, and LEF generation, you will contribute to the enhancement of the performance and reliability of semiconductor IPs. Ensuring compliance wi...

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and highly skilled engineer committed to advancing the field of high-speed analog design. You bring a wealth of experience in designing critical analog and mixed-signal blocks, particularly for cutting-edge PCIe 6 and PCIe 7 or SerDes PHY solutions. Your techn...

As a Senior R&D Engineer at Synopsys, you will play a crucial role in characterizing and modeling standard cells for various technologies and foundries. Your deep knowledge of MOSFET and FINFET technologies will be instrumental in conducting quality analysis of characterized liberty and Verilog models, ensuring accuracy in terms of timing, power, and functionality. By validating characterization and simulation tool versions, you will contribute to the enhancement of our standard cell models and tools" reliability. Your commitment to providing daily status updates and ensuring on-time, high-quality releases will be essential in driving innovation and continuous improvement within our engineer...

You will be responsible for developing block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics. Your role will involve applying an understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs. You will conduct analyses, tests, and verify designs using different tools and techniques to identify and troubleshoot issues. It is essential to stay abreast of new verification methods and work collaboratively with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues. To qualify for this posi...

Expertise in working on memory layout design for advanced nodes (TSMC 3nm, 5nm,), including FinFET architecture and challenges such as variability and manufacturability Expertise in working on address process-dependent effects like electro-migration (EM), IR drop Expertise in optimizing layouts for yield enhancement and manufacturing robustness Expertise in performing debugging of silicon failures and identify layout-related issues Create detailed and optimized physical layouts for memory cells, arrays, and peripheral circuits using tools like Cadence Virtuoso or Synopsys Custom Compiler Perform parasitic extraction and ensure compliance with DRC (Design Rule Check) and LVS (Layout Versus Sc...

You will be responsible for executing internal projects or small tasks within customer projects related to VLSI Frontend, Backend, or Analog design with minimal supervision from the Lead. Your role will involve working as an Individual contributor on tasks such as RTL Design, Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, and Signoff. You will be expected to analyze and complete assigned tasks within the defined domain successfully and on time with minimal support from senior engineers, ensuring quality delivery as approved by the senior engineer or project lead. Quality of deliverables is a key focus, requiring clean delivery of modules that are easy to...

Expertise in working on memory layout design for advanced nodes (TSMC 3nm, 5nm,), including FinFET architecture and challenges such as variability and manufacturability Expertise in working on address process-dependent effects like electro-migration (EM), IR drop Expertise in optimizing layouts for yield enhancement and manufacturing robustness Expertise in performing debugging of silicon failures and identify layout-related issues Create detailed and optimized physical layouts for memory cells, arrays, and peripheral circuits using tools like Cadence Virtuoso or Synopsys Custom Compiler Perform parasitic extraction and ensure compliance with DRC (Design Rule Check) and LVS (Layout Versus Sc...