8 Finesim Jobs

Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable todays needs and tomorrows next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world were living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description Actively contribute to provide Custom Datapath solutions for next generation Memory in advanced CMOS technology nodes. Designing Datapath (custom and/or RTL) Blocks, Full chip Timing Finesim Design closure to meet the specifications and product requirements Work closely with team and actively participate in technical discussions and reviews. Pro-actively get design issues/problems solved. Contribute to or propose innovative design solutions and design methodologies. Qualifications Bachelors/Masters degree in Electronics & Telecommunication/Electrical engineering (VLSI Design) Hands-on design knowledge on both Digital custom, Analog & mixed signal design environment. 4+ years of Experience on IO circuit blocks used in memory products like DDR4, DDR5, LPDDR4, LPDDR5, GDDR5, GDDR6 is desirable. NAND Flash Design knowledge is plus Familiar with custom design methodology & flow, Calibration, JTAG design requirements, understanding of High-speed IO circuit and Datapath design including DLL, Rx, Tx and clocking circuits Knowledge of High Speed layout guidelines, analog layout techniques, including floor-planning, matching, shielding and parasitic optimization Understanding Datapath circuits like pipelining, digital design, STA, fan-out and load estimation, FIFO design etc.. Familiarity with package/board/Power integrity /signal integrity constraints is a plus. Strong communication skills & circuit design knowledge is preferred. Tool knowledge: spice tools: finesim, hspice & other flows Good automation & scripting knowledge is plus. Additional Information Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at [HIDDEN TEXT] to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying. Show more Show less

Responsibilities Design and maintain standard cells for new products based on new technology. Characterize the performance of standard cells and optimize the standard cell design and layout. Characterization and modeling of Standard Cell and semi-Custom cells to provide timing/power model for verification. Quality Analysis of characterized liberty models in terms of Timing, Power and Functionality. Closely collaborate with DTCO team to work on stdcells architecture for emerging technologies. Develop automation test bench/flow/tools to improve the work efficiency and help data analysis. Co-work with international colleagues on developing new verification flows to take on the challenges in DRAM and emerging memory design. Requirements Good understanding of CMOS circuit design Good knowledge of CMOS device physics and layout Experience in any characterization tools (Siliconsmart/Liberate)and Cadence Virtuoso preferred. Experience in Primetime, Solido Analytics, ICC flow is added an advantage. Familiar with analog/digital simulation tools, i.e. HSPICE, HSIM, VerilogHDL, FINESIM, Simvision Experience in Standard Cell design and verification Experience in using Skill, TCL, Perl, Python to do test bench automation and data analysis is a plus Previous work experience in DRAM memory related fields or analog blocks is a plus. Must possess good interpersonal & communication skills and ability to work well in a team

As an ideal candidate, you are a highly motivated and experienced Analog Design Engineer with a passion for developing state-of-the-art analog sensors You have a solid background in custom analog/mixed-signal circuit design, circuit simulations, custom layout, and post-silicon characterization You thrive in a collaborative environment, guiding junior engineers, and liaising with layout teams to achieve optimal engineering solutions Your forward-thinking approach, combined with your extensive technical knowledge, enables you to tackle the unique challenges posed by various target applications You possess a b tech or M Tech degree in Electrical Engineering with 1 years of relevant industry experience or a PhD with relevant Experience Your expertise in advanced process challenges, including ESD and reliability, and your familiarity with tools like PrimeSim, FineSim, and HSPICE, set you apart as a leader in the field What Youll Be Doing: Conceptualizing, designing, and productizing state-of-the-art on-chip Process, Voltage, Temperature, Current, and Droop sensors Developing innovative solutions in the field of on-die monitoring Liaising with the layout team to achieve the best possible engineering solutions Deploying new sensors into test chips and conducting post-silicon characterization Guiding and mentoring junior engineers and tracking their work progress Collaborating with internal teams and external customers to ensure project success The Impact You Will Have: Enhancing the performance, power, area, schedule, and yield of our products Contributing to the reliability and optimization of next-generation intelligent in-chip sensors Driving innovation in on-die monitoring solutions Improving the integration process for customers, leading to faster time-to-market Providing technical leadership and mentoring to junior engineers Ensuring the successful deployment and characterization of new sensors What You'll Need: Strong technical experience in full custom analog/mixed-signal circuit design, simulations, and custom layout Tech Knowledge of custom Analog/AMS design techniques, implementation, and verification Familiarity with advanced process challenges, including ESD and reliability Experience with tools like PrimeSim, FineSim, HSPICE, and Custom Compiler or equivalent schematic layout editor tools Who You Are: A forward-thinking and design-oriented individual A team player with excellent communication, mentoring, and interpersonal skills A problem-solver who can handle moderate scope problems and analyze several factors An established professional with practical knowledge and the ability to resolve a variety of issues Someone who can work under general supervision and achieve day-to-day objectives with moderate impact

As an ideal candidate, you are a highly motivated and experienced Analog Design Engineer with a passion for developing state-of-the-art analog sensors. You have a solid background in custom analog/mixed-signal circuit design, circuit simulations, custom layout, and post-silicon characterization. You thrive in a collaborative environment, guiding junior engineers, and liaising with layout teams to achieve optimal engineering solutions. Your forward-thinking approach, combined with your extensive technical knowledge, enables you to tackle the unique challenges posed by various target applications. You possess a BTech or MTech degree in Electrical Engineering with 1+ years of relevant industry experience or a PhD with relevant experience. Your expertise in advanced process challenges, including ESD and reliability, and your familiarity with tools like PrimeSim, FineSim, and HSPICE, set you apart as a leader in the field. What You'll Be Doing: Conceptualizing, designing, and productizing state-of-the-art on-chip Process, Voltage, Temperature, Current, and Droop sensors. Developing innovative solutions in the field of on-die monitoring. Liaising with the layout team to achieve the best possible engineering solutions. Deploying new sensors into test chips and conducting post-silicon characterization. Guiding and mentoring junior engineers and tracking their work progress. Collaborating with internal teams and external customers to ensure project success. The Impact You Will Have: Enhancing the performance, power, area, schedule, and yield of our products. Contributing to the reliability and optimization of next-generation intelligent in-chip sensors. Driving innovation in on-die monitoring solutions. Improving the integration process for customers, leading to faster time-to-market. Providing technical leadership and mentoring to junior engineers. Ensuring the successful deployment and characterization of new sensors. What You'll Need: Strong technical experience in full custom analog/mixed-signal circuit design, simulations, and custom layout. Technical knowledge of custom Analog/AMS design techniques, implementation, and verification. Familiarity with advanced process challenges, including ESD and reliability. Experience with tools like PrimeSim, FineSim, HSPICE, and Custom Compiler or equivalent schematic layout editor tools.

As an ideal candidate, you are a highly motivated and experienced Analog Design Engineer with a passion for developing state-of-the-art analog sensors. You have a solid background in custom analog/mixed-signal circuit design, circuit simulations, custom layout, and post-silicon characterization. You thrive in a collaborative environment, guiding junior engineers, and liaising with layout teams to achieve optimal engineering solutions. Your forward-thinking approach, combined with your extensive technical knowledge, enables you to tackle the unique challenges posed by various target applications. You possess a BTech or MTech degree in Electrical Engineering with 1+ years of relevant industry experience or a PhD with relevant experience. Your expertise in advanced process challenges, including ESD and reliability, and your familiarity with tools like PrimeSim, FineSim, and HSPICE, set you apart as a leader in the field. What You'll Be Doing: Conceptualizing, designing, and productizing state-of-the-art on-chip Process, Voltage, Temperature, Current, and Droop sensors. Developing innovative solutions in the field of on-die monitoring. Liaising with the layout team to achieve the best possible engineering solutions. Deploying new sensors into test chips and conducting post-silicon characterization. Guiding and mentoring junior engineers and tracking their work progress. Collaborating with internal teams and external customers to ensure project success. The Impact You Will Have: Enhancing the performance, power, area, schedule, and yield of our products. Contributing to the reliability and optimization of next-generation intelligent in-chip sensors. Driving innovation in on-die monitoring solutions. Improving the integration process for customers, leading to faster time-to-market. Providing technical leadership and mentoring to junior engineers. Ensuring the successful deployment and characterization of new sensors. What You'll Need: Strong technical experience in full custom analog/mixed-signal circuit design, simulations, and custom layout. Technical knowledge of custom Analog/AMS design techniques, implementation, and verification. Familiarity with advanced process challenges, including ESD and reliability. Experience with tools like PrimeSim, FineSim, HSPICE, and Custom Compiler or equivalent schematic layout editor tools.

Develop and maintain circuit design methodology flows and documentation. Identify and refine circuit implementations to achieve optimal power, area and performance targets. Propose design and verification strategies that efficiently use simulator features to ensure highest quality design. Oversee physical layout to minimize the effect of parasitic, device stress, and process variation. Collaborate with digital RTL engineers on the development of calibration, adaptation and control algorithms for analog circuits. Present simulation data for peer and customer review. Mentor and Review the progress of junior engineers. Document design features and test plans. Required Qualifications: Bachelor with 2 years experience or MSEE (or PhD) in Electrical Engineering, Computer Engineering, or similar technical field In-depth familiarity with transistor level circuit design - sound CMOS design fundamentals. Silicon-proven experience implementing circuits like bandgap references, voltage regulators. Detailed design experience with high custom logic design Experience optimizing FinFET CMOS layout to minimize the effect of parasitic resistance and capacitance, and to reduce the effects of local device mismatch and proximity effects. Awareness of ESD issues (i.e. circuit techniques, layout). and design for reliability (i.e. electro-migration, IR, aging, etc.). Experience with EDA tools for schematic entry, physical layout, and design verification. High proficiency with spice simulators including HSPICE, Finesim and XA Knowledgeable in Verilog-A and/or System-Verilog for analog behavioral modeling and simulation-control / data-capture. Plus Qualifications: Ability to provide automationfor rapid and dynamic design needs is highly sought-after Experience with STA and cell characterization such as Nanotime, Primetime, SiliconSmart Experienced in STAR or similar extractor to debug extraction issues Extensive programming skills in languages such as Python, Perl, TCL and C/C++

Looking forward towork on conceptualizing, designing and productizing state of the art Monitor IP to be used in SLM monitors realized though ASIC design flow. Work on Architecting sensing elements for on-chip Process, Voltage, Temperature, glitch and Droop monitors for monitoring silicon biometrics. You will be the part of SLM team. Individual should have strong technical experience in full custom mixed-signal circuit design, circuit simulations, working knowledge of custom layout, and pre-post-silicon characterization. Additional responsibilities include: Development of statistical simulation methodologies. Liaising with layout team to achieve best possible design solution. End to end ownership of the designed custom cells. Deployment of new circuits into test chips and post-silicon characterization Architecting new sensors and enhancing existing ones through collaboration with other architects and stakeholders. Building and refining design flows to enhance efficiency and effectiveness. Conducting pre and post-layout simulations and characterization across various design corners. Ensuring designs meet advanced finfet / GAA reliability and aging, reliability and Automotive grade requirements Working closely with the RTL, Verification and Physical Design teams for ensuing integration and Quality. Owning the product from Spec to Silicon report. Preferred skills: Strong custom design experience - specification, circuit design description and schematics. Strong understanding of device Physics and Can work independently and debug and provide circuit solutions. Hands on experience with circuit design & simulation tools, IC design CAD packages - from any EDA vendor Strong understanding of SPICE simulator concepts and simulation methods Familiar with circuit simulation tools like PrimeSim, FineSim, HSPICE or similar Must have prior experience with Custom Compiler or equivalent schematic & Layout editor tools Experience with statistical design methodology like generating and analyzing Monte-Carlo results Awareness of post-layout extraction & simulation, testing in conjunction with silicon validation Demonstrated technical expertise in the productization of advanced technologies.

General Summary: Join Qualcomm's Hardware Engineering team where innovation meets silicon. In this role, you will contribute to the design and characterization of advanced mixed-signal IPs such as DDRIOs, SERDES, ADCs, DACs, and PLLs. This position focuses on developing Verilog behavioral models and performing accurate timing and power characterization using industry-standard tools. You'll be collaborating with cross-functional teams to ensure high-quality deliverables for Qualcomm's world-class chipsets. Key Responsibilities: Develop behavioral models (Verilog, Verilog-MS/real, SystemVerilog) for mixed-signal analog IPs such as DDR-MSIP, DDRIOs, SERDES, ADC/DACs, and PLLs. Perform timing and power characterization using tools like Silicon Smart, HSPICE, FineSim, and NanoSim. Create Liberty (.lib) timing and power models and validate them against transistor-level designs. Develop and maintain self-checking testbenches and test plans for model verification. Conduct functional analysis and verification of modeled IPs using simulators like VCS. Collaborate with AMS teams for analog-digital interface verification and ensure robust modeling practices. Automate model generation and verification workflows using Tcl, Perl, or Skill scripting. Interface with design and verification teams to ensure model accuracy and completeness. Minimum Qualifications: Bachelor's degree in Electrical/Electronics Engineering, Computer Science, or related field and 3+ years of relevant hardware modeling experience OR Master's degree and 2+ years of experience OR PhD and 1+ year of experience. Required Skills & Experience: 5+ years of experience with timing/power characterization and view generation tools (e.g., Silicon Smart, HSPICE, FineSim). Strong understanding of mixed-signal analog IP design and functionality. Expertise in Verilog and Verilog-AMS behavioral modeling. Hands-on experience with simulation and verification tools such as VCS. Experience with Liberty file format and creating timing/power views. Knowledge of AMS verification environments is a plus. Strong scripting skills in Tcl, Perl, and/or Skill for automation. Excellent problem-solving, collaboration, and communication skills.