4.0 - 8.0 years

0 Lacs

karnataka

On-site

Job Description You are required to be an experienced DFT Engineer with a strong background in Scan, ATPG, and MBIST for SoC/ASIC designs. Your main responsibilities will include implementation, pattern generation, and verification of DFT features to ensure high test coverage and silicon readiness. Key Responsibilities - Implement and verify Scan, ATPG, and MBIST for complex SoCs. - Perform pattern generation, coverage analysis, and debug. - Integrate and validate MBIST with appropriate memory test algorithms. - Coordinate with RTL and Physical Design teams for smooth DFT integration and signoff. - Develop automation scripts to streamline DFT flows. Qualification Required - Minimum 4 years o...

Posted 1 day ago

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Dft Engineer HCLTech

2.0 - 7.0 years

6 - 15 Lacs

Hyderabad, Chennai, Bengaluru

Work from Office

Role & responsibilities DFT Engineer Must-Have: •Tools: Synopsys DFT Compiler, Tessent, Mentor TestKompress, Tetramax, Fastscan •Techniques: •Scan Insertion (ATPG) •Boundary Scan (JTAG) •MBIST, LBIST •Compression techniques •Stuck-at, Transition fault models •Simulation and validation of test vectors •DFT signoff and coverage reports •STA constraint generation for test modes Nice-to-Haves: •Tapeout experience •Knowledge of low-power test techniques •Integration of DFT at SoC level Common Green Flags Across Roles: •Product or IP ownership •Clear mention of project responsibilities (not just team contribution) •Mention of tapeouts or silicon-proven designs •Stable employment history (avoiding ...

Posted 5 months ago

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