About this opportunity We are seeking a Tech Lead FPGA Designer to join the Ericsson Silicon organization. In this pivotal role, you will provide technical leadership to a group of dedicated engineers committed to developing world-class Radio and RAN Compute products. You will lead the FPGA team in designing, integrating, and optimizing complex systems for high-efficiency data transfer and processing with embedded subsystems. As part of our global organization, youll collaborate with talented teams across our various sites. We are committed to Agile principles, fostering a collaborative and innovative work environment that encourages creativity, teamwork, and strategic thinking. What you will do Lead the design and implementation of advanced FPGA-based Radio and RAN Compute solutions. Lead efforts to optimize FPGA designs for maximum performance, power efficiency, and cost-effectiveness. Guide hardware and software engineers in the integration of FPGA solutions into larger systems, ensuring seamless collaboration and execution. Apply and refine industry-standard tools and methodologies for FPGA development and implementation. Conduct research and provide thought leadership on the latest advancements in FPGA technology, including AI and Machine Learning trends in academia and industry. Author key documents such as comprehensive requirements and design specifications Lead design reviews and champion innovative ideas to enhance FPGA solutions and drive technological advancement. Collaborate closely with FPGA suppliers to ensure alignment and integration Work closely with verification and lab engineers, as well as hardware design and verification teams, to ensure comprehensive testing and validation Provide mentoring and guidance to team members You will bring 10+ years of experience in FPGA development, including leadership roles. Extensive knowledge of: o FPGA technology, design environments, and advanced design methodologies. o FPGA design tools (e.g., Vivado, Quartus, or similar) and emerging technologies. o Hardware description languages (HDL), such as Verilog or VHDL. Proven expertise in various communication protocols such as Ethernet with IPSec/MACSEC, PCIE gen6, I2C/I3C, SPI, etc. Advanced proficiency with scripting languages such as Python, Tcl, shell scripting, etc. Strong familiarity with hardware architecture and digital signal processing, with a strategic vision Exceptional problem-solving and analytical skills, with a track record of driving innovation. Excellent English verbal and written communication skills, with the ability to convey complex ideas clearly and persuasively. High self-motivation and the ability to work independently while leading and inspiring teams. A track record of successful cross-team and cross-site cooperation, including leadership roles. A Bachelor s degree in Electrical or Computer Engineering or equivalent. Primary country and city: India (IN) || Bangalore Req ID: 766859

About this opportunity We are seeking a Tech Lead FPGA Designer to join the Ericsson Silicon organization. In this pivotal role, you will provide technical leadership to a group of dedicated engineers committed to developing world-class Radio and RAN Compute products. You will lead the FPGA team in designing, integrating, and optimizing complex systems for high-efficiency data transfer and processing with embedded subsystems. As part of our global organization, youll collaborate with talented teams across our various sites. We are committed to Agile principles, fostering a collaborative and innovative work environment that encourages creativity, teamwork, and strategic thinking. What you will do Lead the design and implementation of advanced FPGA-based Radio and RAN Compute solutions. Lead efforts to optimize FPGA designs for maximum performance, power efficiency, and cost-effectiveness. Guide hardware and software engineers in the integration of FPGA solutions into larger systems, ensuring seamless collaboration and execution. Apply and refine industry-standard tools and methodologies for FPGA development and implementation. Conduct research and provide thought leadership on the latest advancements in FPGA technology, including AI and Machine Learning trends in academia and industry. Author key documents such as comprehensive requirements and design specifications Lead design reviews and champion innovative ideas to enhance FPGA solutions and drive technological advancement. Collaborate closely with FPGA suppliers to ensure alignment and integration Work closely with verification and lab engineers, as well as hardware design and verification teams, to ensure comprehensive testing and validation Provide mentoring and guidance to team members You will bring 10+ years of experience in FPGA development, including leadership roles. Extensive knowledge of: o FPGA technology, design environments, and advanced design methodologies. o FPGA design tools (e.g., Vivado, Quartus, or similar) and emerging technologies. o Hardware description languages (HDL), such as Verilog or VHDL. Proven expertise in various communication protocols such as Ethernet with IPSec/MACSEC, PCIE gen6, I2C/I3C, SPI, etc. Advanced proficiency with scripting languages such as Python, Tcl, shell scripting, etc. Strong familiarity with hardware architecture and digital signal processing, with a strategic vision Exceptional problem-solving and analytical skills, with a track record of driving innovation. Excellent English verbal and written communication skills, with the ability to convey complex ideas clearly and persuasively. High self-motivation and the ability to work independently while leading and inspiring teams. A track record of successful cross-team and cross-site cooperation, including leadership roles. A Bachelor s degree in Electrical or Computer Engineering or equivalent. Why join Ericsson? What happens once you apply? Primary country and city: India (IN) || Bangalore Req ID: 766859

Education: B.E in E l e ctronics & Communication E ng ineering Tessolve Semicon ductors a venture of He ro Electronix, par t of $ 5B Hero Group companies a Design and Test Engineering Service Company providing End to End Solutions from Product Engineering, Software, Hardware, Wireless, Automotive and Embedded Solutions. Currently we are 2300+ employees worldwide. We are Global Multi- National Company having Engineering and Sales presences in India, Malaysia, Singapore, USA, UK, Europe, and China. Tessolve has strategic and sustainable growth plan to ensure the business stability to our valued customers and to protect the career of our employees even under disturbed Business situations. Technical Skillset Required: Technologies with sound knowledge WLAN IEEE802.11 a/b/g/n/ ac / ax Test experience. Ethernet & Wired networking (added advantage) Independent Project handling with analytical ability Testing Experience Functional / Performance / IOT / Certification WLAN tests Protocols/Layers with good theoretical & practical knowledge Sound knowledge on Layer 1, 2, 3, IEEE802.11 a/b/g/n/ ac / ax Knowledge on WPA2/WPA3, MU-MIMO, OFDMA, Beamforming, Roaming etc Traffic Generators Understating and Usage of Traffic generator tools like Spirent / Ixia / Chariot/ Veriwave . Knowledge on RFC2544, RFC2889, RFC3918 tests etc. Traffic Analyzers Wireshark, Ethereal, airopeak / omnipeak Operating Systems Windows 10/XP/Win7, Linux Automation Scripting Knowledge of Automation Scripts is mandatory Python / Perl / TCL.

Responsible for developing & testing of software Responsible for generating documents, such as Requirements Spec, design, user-guide, API spec, etc., Skills Must have Candidate should have 7+ yrs experience Experience: Experience in designing complex multithreaded Performant SW Experience in designing SW API interfaces. Experience in C/C++ programming Experience with Multi-threaded software development in Linux environment Experience with Embedded IP subsystems e.g. Ethernet / PCIe / SPI / I2C / USB / GPIO / Memory architectures /DDR/SDRAM/DMA Experience with development of software targeted for x86, standalone and RTOS platforms Experience in low level driver development, register interface programming, general algorithms and data structures, bootloaders/Uboot Experience working with and integrating open-source software Strong debugging skills at device and board level using JTAG debuggers Experience in Software programming for FPGAs is an advantage Scripting language experience like Perl, Python or TCL Nice to have Excellent interpersonal, written and verbal communication skills Excellent communication, problem solving and analytical skills Education: B.tech/M.Tech in CSE/IT/ECE/EEE/E&I

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a team first organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you re looking for.Responsibilities & Skills Do you have a passion for invention and self-challenge? This position gives you an opportunity to learn and participate in one of the most cutting-edge projects that Lattice s Silicon Engineering team has embarked upon to date. We are validating building blocks in FPGA on board level to ensure functionality and performance aspect of Design intent. FPGA consists of various IPs as a building block such as SERDES(PMA/PCS), Memory DDR(DDR4, LPDDR4, DDR5 etc), DPHY, PLL, DSP, Fabric, I/O etc. As a Silicon Design Validation engineer, you will have an opportunity to learn and train yourself on how to validate one/or many of the building blocks within the FPGA. And also, you will be able to acquire knowledge on process/methodology required for validating certain IPs from planning to completion. While you are working on those, you will be exposed to cutting edge equipment and advanced boards as well as Various SW/tools/scripts. What you re going to be exposed to and learn: The ideal candidate is highly motivated in developing a career in Silicon Design Validation engineering. You will get significant exposure and training in the following areas: Chance to learn FPGA and it s build block such as SERDES(PMA/PCS), Memory DDR(DDR4, LPDDR4, DDR5 etc), DPHY, PLL, DSP, MIPI, Fabric, I/O etc but not limited. Validate and characterize various IPs from silicon arrival to release to production. Develop validation and characterization plans for certain IP, bench hardware and software. Develop test logic RTL to achieve intended validation/characterization test. Drive new silicon product bring-up, validation, debug to asses IP functionality/performance. Characterizing data sheet parameters. Analyzing the measured data with statistical view. Data sheet preparation etc. Serve as the central resource with design, verification, manufacturing, test, quality and marketing/apps as the product(s) move Silicon arrival to product release. Supporting customer issues as required to resolve issues found after product release You Have 5+ years of experience Electrical Engineering degree with a strong desire to pursue an engineering career in Silicon Design Validation Expertise in High Speed Serdes Interface characterization and protocol compliance testing such as PCIe / Ethernet / SDI / CoaXpress / JESD204 , MIPI D-PHY, MIPI CSI/DSI-2, USB and DisplayPort/HDMI etc. Expertise in high speed board design and signal integrity evaluation/debug. Expertise in Verilog/VHDL and design implementation using FPGA development tools. Expertise in test automation development using programming languages such as Python, Perl. Knowledge of statistical analysis concepts and use of analysis tools such as JMP, R. Proficiency with bench equipment for device characterization such as BERT, VNA, Oscilloscopes, Protocol Exerciser/Analyzers. Exposure on FPGA(emulation/prototyping etc) Strong written and verbal communication skills to work with cross-functional team Self-motivated and proactive with critical thinking. Good problem solving and debugging skills.

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a team first organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you re looking for.Responsibilities & Skills Do you have a passion for invention and self-challenge? This position gives you an opportunity to learn and participate in one of the most cutting-edge projects that Lattice s Silicon Engineering team has embarked upon to date. We are validating building blocks in FPGA on board level to ensure functionality and performance aspect of Design intent. FPGA consists of various IPs as a building block such as SERDES(PMA/PCS), Memory DDR(DDR4, LPDDR4, DDR5 etc), DPHY, PLL, DSP, Fabric, I/O etc. As a Silicon Design Validation engineer, you will have an opportunity to learn and train yourself on how to validate one/or many of the building blocks within the FPGA. And also, you will be able to acquire knowledge on process/methodology required for validating certain IPs from planning to completion. While you are working on those, you will be exposed to cutting edge equipment and advanced boards as well as Various SW/tools/scripts. What you re going to be exposed to and learn: The ideal candidate is highly motivated in developing a career in Silicon Design Validation engineering. You will get significant exposure and training in the following areas: Chance to learn FPGA and it s build block such as SERDES(PMA/PCS), Memory DDR(DDR4, LPDDR4, DDR5 etc), DPHY, PLL, DSP, MIPI, Fabric, I/O etc but not limited. Validate and characterize various IPs from silicon arrival to release to production. Develop validation and characterization plans for certain IP, bench hardware and software. Develop test logic RTL to achieve intended validation/characterization test. Drive new silicon product bring-up, validation, debug to asses IP functionality/performance. Characterizing data sheet parameters. Analyzing the measured data with statistical view. Data sheet preparation etc. Serve as the central resource with design, verification, manufacturing, test, quality and marketing/apps as the product(s) move Silicon arrival to product release. Supporting customer issues as required to resolve issues found after product release You Have 2+ years of experience Electrical Engineering degree with a strong desire to pursue an engineering career in Silicon Design Validation Knowledge in High Speed Serdes Interface characterization and protocol compliance testing such as PCIe / Ethernet / SDI / CoaXpress / JESD204 , MIPI D-PHY, MIPI CSI/DSI-2, USB and DisplayPort/HDMI etc. Knowledge in high speed board design and signal integrity evaluation/debug. Knowledge in Verilog/VHDL and design implementation using FPGA development tools. Knowledge in test automation development using programming languages such as Python, Perl. Knowledge of statistical analysis concepts and use of analysis tools such as JMP, R. Exposure on bench equipment for device characterization such as BERT, VNA, Oscilloscopes, Protocol Exerciser/Analyzers. Exposure on FPGA(emulation/prototyping etc) Strong written and verbal communication skills to work with cross-functional team Self-motivated and proactive with critical thinking. Good problem solving and debugging skills.

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a team first organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you re looking for.Responsibilities & Skills Do you have a passion for invention and self-challenge? This position gives you an opportunity to learn and participate in one of the most cutting-edge projects that Lattice s Silicon Engineering team has embarked upon to date. We are validating building blocks in FPGA on board level to ensure functionality and performance aspect of Design intent. FPGA consists of various IPs as a building block such as SERDES(PMA/PCS), Memory DDR(DDR4, LPDDR4, DDR5 etc), DPHY, PLL, DSP, Fabric, I/O etc. As a Silicon Design Validation engineer, you will have an opportunity to learn and train yourself on how to validate one/or many of the building blocks within the FPGA. And also, you will be able to acquire knowledge on process/methodology required for validating certain IPs from planning to completion. While you are working on those, you will be exposed to cutting edge equipment and advanced boards as well as Various SW/tools/scripts. What you re going to be exposed to and learn: The ideal candidate is highly motivated in developing a career in Silicon Design Validation engineering. You will get significant exposure and training in the following areas: Chance to learn FPGA and it s build block such as SERDES(PMA/PCS), Memory DDR(DDR4, LPDDR4, DDR5 etc), DPHY, PLL, DSP, MIPI, Fabric, I/O etc but not limited. Validate and characterize various IPs from silicon arrival to release to production. Develop validation and characterization plans for certain IP, bench hardware and software. Develop test logic RTL to achieve intended validation/characterization test. Drive new silicon product bring-up, validation, debug to asses IP functionality/performance. Characterizing data sheet parameters. Analyzing the measured data with statistical view. Data sheet preparation etc. Serve as the central resource with design, verification, manufacturing, test, quality and marketing/apps as the product(s) move Silicon arrival to product release. Supporting customer issues as required to resolve issues found after product release You Have 5+ years of experience Electrical Engineering degree with a strong desire to pursue an engineering career in Silicon Design Validation Expertise in High Speed Serdes Interface characterization and protocol compliance testing such as PCIe / Ethernet / SDI / CoaXpress / JESD204 , MIPI D-PHY, MIPI CSI/DSI-2, USB and DisplayPort/HDMI etc. Expertise in high speed board design and signal integrity evaluation/debug. Expertise in Verilog/VHDL and design implementation using FPGA development tools. Expertise in test automation development using programming languages such as Python, Perl. Knowledge of statistical analysis concepts and use of analysis tools such as JMP, R. Proficiency with bench equipment for device characterization such as BERT, VNA, Oscilloscopes, Protocol Exerciser/Analyzers. Exposure on FPGA(emulation/prototyping etc) Strong written and verbal communication skills to work with cross-functional team Self-motivated and proactive with critical thinking. Good problem solving and debugging skills.

-Linux application programming Linux device driver development Embedded C, MMU, Cache policies Excellent debugging skills at kernel and user space and exposure to different debugging tools Knowledge on PCIe, Ethernet, TCP, I2C protocols, DMA framework is a plus. Make files Skills Must have Candidate should have 5-8yrs experience Proficient in C and embedded systems. Experience in Linux driver development (PCIe/USB/Ethernet) and application development. PCIe driver development experience. DMA client/controller driver development experience Hands-on experience with Configuration Management tool like GIT, Perforce. Have an interest to constantly learn and share new findings. A quality mindset, ability for strategic thinking and a drive to always improve. Self-motivated Nice to have B.tech/M.Tech in CSE/IT/ECE/EEE/E&I

[{"Posting_Title":"Sr. PLC Programmer" , "Is_Locked":false , "City":"Pune City" , "Industry":"Industrial" , "Job_Description":" Position Overview We are seeking an experienced Senior PLC Programmer todesign, develop, and maintain advanced control systems for automated industrialprocesses. The ideal candidate will have a proven track record in PLCprogramming, system integration, and troubleshooting across diverse industrialenvironments. This role requires hands-on expertise with major PLC platforms,strong project management skills, and the ability to collaborate withcross-functional teams to deliver robust automation solutions Key Responsibilities Design, program, test, and commission PLC-based control systems for industrial automation projects Develop and modify PLC programs using languages such as Ladder Logic, Structured Text, Function Block Diagram, and Sequential Function Chart Integrate PLCs with HMI (Human-Machine Interface) and SCADA (Supervisory Control and Data Acquisition) systems to enable efficient process monitoring and control Analyse project requirements, interpret electrical schematics, and collaborate with engineers and technicians to deliver tailored automation solutions Troubleshoot, debug, and optimize PLC programs to ensure reliability, safety, and efficiency of automated systems Oversee project timelines, coordinate resources, and provide technical guidance to junior programmers or technicians Maintain comprehensive documentation of programming changes, system configurations, and project deliverables Stay updated on emerging technologies and best practices in industrial automation and PLC programming Ensure all work adheres to relevant safety standards and industry regulations Required Qualifications Bachelor\u2019s degree in electrical engineering/Automation, Computer Engineering Minimum 6 years of hands-on experience in PLC programming, commissioning, and maintenance of automated systems in industrial settings Proficiency with major PLC platforms (e.g., Siemens, Allen-Bradley/Rockwell, Schneider Electric) and associated programming environments (e.g., TIA Portal, RS Logix) Strong understanding of industrial networking protocols (e.g., Ethernet/IP, Modbus) and integration with HMI/SCADA systems In-depth knowledge of electrical circuits, control systems, and industrial instrumentation Demonstrated experience in project management, including planning, resource coordination, and meeting deadlines Excellent problem-solving, troubleshooting, and analytical skills Strong verbal and written communication skills for effective collaboration and documentation Preferred Skills Experience with software development in C/C++, Python, or Java for advanced automation and system integration tasks Familiarity with AutoCAD or similar software for creating and interpreting electrical schematics Prior experience in manufacturing, process industries, or similar industrial environments Ability to mentor and provide technical leadership to junior staff ","Job_Type":"Full time","Job_Opening_Name":"Sr. PLC Programmer" , "State":"Maharashtra" , "Country":"India" , "Zip_Code":"411001" , "id":"481259000052379286" , "Publish":true , "Date_Opened":"2025-05-21" , "Keep_on_Career_Site":false}]

Motorola Solutions is a world leader in the field of professional mobile communications systems with an impressive heritage of technological innovations and a global base of installed systems. The groups main business is the implementation of mission critical digital mobile communication systems for Government & Public Safety Communications customers. Join to the team providing Solution Architecture for Unified Communications customers for EMEA/APAC/LATAM regions. You will be part of a multi-disciplined project team dedicated to working on the design and delivery of complex mission-critical voice and data systems. The systems may be used directly by our customers or by Motorola Solutions to deliver Managed Services to our customers. You will work in the post-sales phases of projects as well as support multiple projects in parallel, depending on size and complexity. Job Description Technical Authority providing overall technical leadership for the project implementation. Works with customer to understand overall solutions needs and functionality of MSI and third party applications. Takes ownership of the technical solution from pre and post-sale. Works with the project manager to develop the project deployment schedule. Identify technical risks of the projects and works with PM on mitigation plans. Identify customer expectation mismatch to how products work and works with PM on mitigation plans. Technical counterpart with the PM in third party vendor, customer, and internal facing meetings. Owns project change control as it pertains to the overall technical solution. Basic Requirements Qualifications: Bachelors Degree (BSEE/BSCE preferred) Knowledge in Unified Communications in a radio communication systems or broadband/LTE Good understanding, and working knowledge in IP networking, network design methodologies & troubleshooting (Ethernet, TCP/IP, L2/L3, MPLS) Understanding of virtualization and containerization. Experience directly working with end-user customers is desirable Excellent communications skills and the ability to present complex topics to nontechnical audiences. Self motivated and able to maintain focus in a pressured environment Certifications through CompTIA Network+, Juniper JNCIA-Junos, Nokia NRS1, CCNA or similar are a plus Responsibilities: Bill of Materials Hardware & Software Ordering Data Center design: IP networks, Rack layouts High Level Architecture documentation Support Low Level design Security Assessments Security Architecture documentation Change Requests Evaluation Customer meetings Design workshops Customer Queries support Pre-Sales support to Architecture workshops, RFP evaluation and response. Also, to reward your hard work you ll get: Competitive salary package Medical Insurance Life insurance Employee Stock Purchase Plan Flexible working hours Strong collaborative culture Comfortable work conditions Travel opportunities Travel Requirements None Relocation Provided International Position Type Experienced

Arista Networks is an industry leader in data-driven, client-to-cloud networking for large data center, campus and routing environments. Arista is a well-established and profitable company with over $5 billion in revenue. Arista’s award-winning platforms, ranging in Ethernet speeds up to 800G bits per second, redefine scalability, agility, and resilience. Arista is a founding member of the Ultra Ethernet consortium. We have shipped over 20 million cloud networking ports worldwide with CloudVision and EOS, an advanced network operating system. Arista is committed to open standards, and its products are available worldwide directly and through partners. At Arista, we value the diversity of thought and perspectives each employee brings. We believe fostering an inclusive environment where individuals from various backgrounds and experiences feel welcome is essential for driving creativity and innovation. Our commitment to excellence has earned us several prestigious awards, such as the Great Place to Work Survey for Best Engineering Team and Best Company for Diversity, Compensation, and Work-Life Balance. At Arista, we take pride in our track record of success and strive to maintain the highest quality and performance standards in everything we do. Job Description Who You’ll Work With You will work with software development engineers, hardware engineers, field support engineers, product managers, and software test engineers to analyse customer requirements and use cases, gather technical details, create software test plans, and validate that the product meets our customer’s requirements. You will also work with our customer support and engineering teams to help address escalated customer issues by reproducing, and debugging those in the lab. The role will provide opportunities to create real impact in the rapidly growing Software defined (SD) branch, SD-WAN, Cloud IT services, and virtualization technologies. What You’ll Do Arista Networks is looking for world-class Software Test Engineers (aka System Test engineers) to help us in building the highest quality networking products. If you love networking. If working on complex & scaled out network topologies makes you excited. If you like to challenge yourself to find the hard-to-find bugs and if troubleshooting & debugging network and system problems gives you a thrill, this role is tailor made for you. At Arista, you’ll bring your intelligence, creativity, and drive every day & work with our products exactly how they are going to be used by our end customers and while doing so, make sure that the products are going to work every time. Your job is to find the hard bugs, the ones not easily exposed by the developers’ automated unit and product level tests. You will NOT spend your time running manual regressions of mind numbing, 1000 page test plans, because Arista’s developers automate all the basic functional and integration tests. Courtesy our super collaborative work environment, you’ll spend your time embedded deeply with multiple engineering teams, working side by side with the developers, POC engineers, account teams, working together as one team and do all of it to help us to explore, find and fix software problems before they can reach the customers. We take quality seriously and we invite you to be a champion of software quality!! Qualifications Experience & Education: BE/ B.Tech/ME/ M. Tech with networking industry experience. Proven expertise in creating test methodologies and writing test plans. Strong knowledge in one or more of the following areas: Ethernet, RSTP/ MSTP, VLANs, IP Routing, TCP/IP, OSPF, IS-IS, BGP, IGMP, PIM SM/SSM, QoS, L2-L3 protocols, Platform validation, HA, QOS, network management. Experience with IXIA and/or Spirent test tools desired. Work with the developers on your team in creating their plans for automated tests to complement the exploratory testing that you perform. Participate in functional specification and software design reviews held by your team and provide customer centric input. Work in a highly productive environment along with best of the engineers on Linux platform that cuts a typical development cycle by order of magnitude with a laser focus towards quality. Use every means possible to find the bugs in the software and/or hardware being developed by your team. Write test plans to validate Arista features and products. Design test network topologies to validate functionality, performance, stability and scalability of features and products. Execute test plans to verify all aspects of the product. Identify defects and validate resolution. Work as an agile member of a combined development and test team, running in short cycles to develop functional software in quick iterations. Additional Information Arista stands out as an engineering-centric company. Our leadership, including founders and engineering managers, are all engineers who understand sound software engineering principles and the importance of doing things right. We hire globally into our diverse team. At Arista, engineers have complete ownership of their projects. Our management structure is flat and streamlined, and software engineering is led by those who understand it best. We prioritize the development and utilization of test automation tools. Our engineers have access to every part of the company, providing opportunities to work across various domains. Arista is headquartered in Santa Clara, California, with development offices in Australia, Canada, India, Ireland, and the US. We consider all our R&D centers equal in stature. Join us to shape the future of networking and be part of a culture that values invention, quality, respect, and fun. Show more Show less

Scope of Role Responsible for complete technical leadership across the team, in terms of present and future control / mechatronic system development Expert working knowledge of all types of control systems required to operate lateral, longitudinal and motion control systems within vehicles, combined with a solid foundation of EE & System engineering Strong knowledge of associated hardware systems is also desired Chassis Control Systems team is responsible for multiple ECU commodities and their advanced integration in to Powertrain & ADAS systems Additional responsibilities include design, development of technical specification and requirements control, testing and integration for delivery on all Chassis modules Candidate requires to be a highly motivated and hands-on team player, with exceptional attention to detail, diligence, a positive attitude and the ability to communicate well The fast-paced development provides a challenging environment suited to an engineer who can quickly develop skills in new areas, and liaise with and drive other engineers within a multidisciplinary/global team Our customers expect high standards and we require team members capa ble of meeting such demands ContactsEngineering, Research & Development / Customer & Client Management / Offshore teamsArea of Re sponsibility Work alongside the Module leader & Domain leader to guide a cross functional global team to collectively deliver all aspect of Chassis controls systems in terms Responsible to lead root cause analysis on issues identified during validation and veh icle builds, in terms of HW and SW elements Take responsibility for resolving issues on current production and development vehicl es with a strategic approach to close out in a timely manner Design and Develop new and existing diagnostic artefacts in the con text of Chassis system commodities Identify opportunities to lead development of supplier competency with regard to diagnostic des ign and module integration Actively seek technical improvement opportunities and lead the tech/integration team with improvement w ork streams Support complete manufacturing integration and support Overlook Functional requirements, Interface agreements, Netwo rk architecture and protocols Support Module Lead and associated LE for issue analysis and fault finding Upskilling team members in robust issue resolution and technical prevent recurrence Support Integration team leader in managing offshore teams Condu ct EOL & AS Process ReviewsKnowledge / Experience Good understanding of the structure in classic Autosar and knowledge of diagnos tics components like DEM, DCM Understanding of automotive CAN, LIN, Ethernet, Flexray and DoIP Proven capability of analysing v ehicle and device level logs in CANalyzer or Wireshark for determining any diagnostic compliance or non-compliance issues Very go od knowledge about industry standards and core domains like HW, SW, Process and methodologies used in automotive ECU and system design Collaborate with engineers on software and hardware changes, solutions and requirements Be proficient in software developme nt workflows able to compile software, change parameters, investigate issues with autonomy Good skills with SDLC/SAFe, Black bo x development and basic SW requirements Previous experience of OEM or tier one automotive systems or components / ECU Understan ding the importance of cost, weight, quality and risk and how it affects the commodities owned and the vehicle programmes the commodities are used on Experience of delivering designs to time, weight and cost targets Supplier management, comfortable with unde rstanding and implementing DFM requirements within the project scope Documentation of Technical Specifications, DFMEA, DVP, Timin g Plans, Minutes and Actions of Meetings Experience in Automotive protocol: CAN(LS/HS/FD), UDS, OBD-2, LIN Knowledge or prior experience of working with vehicle architecture team in an established OEM Understanding of the concepts behind DTC creation and DID/PID assignment based on the hardware and software layout Experience of requirement cascade tools like DOORS, Code beamer etc Experience of issue management tools like JIRA, RTC etc Nice to Have: previous experience on Chassis System Competences Profi cient in all areas of System Development covering the complete Systems V cycle

Hands on strong experience in C coding preferably in Automotive Domain, for a non-OS platform. Experience in microcontrollers and lowlevel sw to test the HW elements Strong understanding of Ethernet protocols and Ethernet switch architectures. Familiarity with hardware-software co-design and FPGA/ASIC development. Experience with network performance analysis and optimization tools. Knowledge of real-time operating systems (RTOS) and embedded systems. Strong knowledge on peripherals & programming on SPI, I2C, PCI, ethernet.

Job Description MediaTek’s creates innovations for future wireless communication system and influences ecosystem by participating global standardization bodies. The MediaTek’s ISD Automotive Technology team is revolutionizing its cutting-edge Wireless, Multimedia, AR/VR/XR, Computer Vision, Generative AI Technologies, and working closely with global Automakers/Tier-1s, consortiums, and creating the safer roads and transportation with evolution of Automotive Infotainment, ADAS/Autonomous Driving and Telematics products. MediaTek’s Automotive Technology team is looking for an experienced Engineers to understand OEMs/Tier1s requirements, architect and develop various platform SW features to enable MediaTek’s most advanced Automotive products. Requirement Professional Experience: 3 to 15 years Technical Skillset BSP/Platform SW development (PMIC/DDR/Clock, high/low speed interfaces such as UART/I2C/SPI/USB/PCIe/Ethernet etc. Experience in UEFI/Kernel driver development, Hypervisors, Virtual Machines (VMs), Virtual driver development including data isolation and permission management. Optimize boot flow, power consumption, thermal management, and overall system performance. Experience in Automotive Safety concepts, and security threat analyses to meet ISO26262, ISO21434 and ASPICE process. Additional Skills The idle candidate might have demonstrated ability to work with engineers/partners/customers across different geographies and contribute to large-scale SoC SW product development and customer support. Hands-on technical lead/engineer who is not hesitant to dig into the details where needed to get first-hand knowledge of the issues and play an active and personal role in steering team success Exposure to one or more of below technology areas is a plus: Multiprocessor Architecture, ARM processors, Virtualization technologies across CPU and Peripherals, hardware accelerators Device driver development in one or more operating systems and platforms including Linux/QNX/RTOS/Android. Involvement in pre-sil/post-sil environments including early emulation/simulation, SoC bring up, post-silicon validation and troubleshooting. Show more Show less

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! We are now looking for highly driven and innovative ASIC / Hardware Engineers. We are looking for bright engineers across our hardware engineering groups to help us Architect, Design and verify our next generation GPUs, CPU and SoCs meant to accelerate the performance of Data Center, Machine Learning, Autonomous Driving, Ray Tracing and many more exciting applications. You will get to work on high performance GPU / SOC/ CPU across Memory sub-systems, Graphic processing units, NOC based Interconnect Fabric, High speed IO's etc. What You'll Be Doing Work on hardware models of different levels of extraction, including performance models, RTL test benches and emulators to find performance bottlenecks in the system. Work closely with the architecture and design teams to explore architecture trade-offs related to system performance, area, and power consumption. Understand key performance use cases or the product. Develop workloads and test suites targeting graphics, machine learning, automotive, video, compute vision applications running on our products. You will be responsible to make architectural trade-offs based on feature/performance/power requirements, analyse system implications, come up with the micro-architecture, implement RTL, drive the verification, close timing, and support silicon validation. Developing test plans, tests and verification infrastructure for complex IP's/sub-system/SOC's. Creating verification environment using UVM methodology and reusable bus functional models, monitors, checkers and scoreboards. Driving functional coverage driven verification closure. Develop and enhance timing analysis/signoff work-flow from frontend (pre-layout) to backend (post-layout) at both chip and block level. Develop custom timing scripts using tcl/primetime for clock skew analysis, special circuits such as clock dividers, core logic IO macros interfaces such as PCI-E, Frame-Buffer/Memory, HDMI, etc. Chip level Integration, physically partitioning and floor planning along with Physical Verification and EM IR Drop You will be responsible for the design and implementation of state-of-the-art designs in test access mechanisms, IO BIST, memory BIST and scan compression. In addition, you will help develop and deploy DFT methodologies for our next generation products. Be apart of innovation to strive improve the quality of DFT methods. Work with architects, designers and post-silicon teams. What We Need To See BTech/MTech with 2+ years of experience in micro-architecture, RTL development of complex designs. Possess strong digital design fundamentals. Preferably have a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor planning, ECO, bring up and lab debug is a prerequisite for this role. If you have experience in at least a few of the following skills, we will have an excellent match for our needs: GPU / CPU / SOC Performance verification and analysis. CPU, Memory controller, Bus Interconnect, Cache coherency IP / SOC Design, Micro-architecture across High Speed IO controller (UFS/PCIE/ XUSB), Network on Chip / 10G Ethernet MAC and (or) Switch IP / SOC Graphics Processing Unit (GPU Design & Verification) BOOT and Power management features for complex SOC’s FPGA Prototype with prior experience in HAP Good debugging and analytical skills. Good interpersonal skills and ability to work as an excellent teammate Excellent communication skills to collaborate with cross-cultural teams and work in a matrix organization With highly competitive salaries and a comprehensive benefits package, NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people in the world working for us. If you're creative and independent, with a genuine real passion for technology, we want to hear from you. JR1978791 Show more Show less

About Airties At Airties we are on a mission to empower broadband operators to deliver a better-connected home experience for their subscribers. We have an exciting story to tell, and we want you to help us tell it! Airties offers broadband operators advanced Wi-Fi solutions and services to allow them bring an improved user experience for their subscribers. The Airties portfolio includes Smart Wi-Fi software, a cloud-based experience management platform with its companion app and data engine. Our company also offers expert, bespoke engineering and testing services. Globally, Airties is the most widely deployed provider of Smart Wi-Fi solutions to network service providers and our technologies are driving a better-connected user experience in more than 35 million homes. Introduction Airties is looking for a Field Application Engineer (FAE) in India. An FAE is the primary technical point of contact to Airties customers across APAC and Australia, accommodating different time zones. This is a multi-faceted role that supports product pre-sales, acceptance, launch and post deployment phases, requiring communication internally and externally at all levels, providing fast and high quality response to customers and being the customer advocate to internal teams. What you will do: Provide onsite installations, product trials and deployments, and other professional services to Airties customers. Work with customers in the field cooperating with Airties Sales, Project, Product and Engineering teams Support sales efforts by explaining current products and solutions, sending samples, conducting trials and proof-of-concepts Escalate product customization and localization needs of the customer to Product, Engineering, and Technical Support management After product release, take responsibility for recording, tracking and handling defects and technical feedback from the customer. Conduct first level root-cause analysis, issue replication and answer technical questions real time on site and escalate appropriately Provide timely and effective resolution to support requests based on internal and external service level agreements (SLA) Work closely with Engineering teams to investigate, assign, and resolve defects. Deploy software defect fixes at customer sites. · Document each customer issue/request using Airties ticket management system Provide ongoing, regular updates to customers to keep them apprised of progress toward problem resolution Respond to requests for technical information and assistance in a timely and professional manner Provide regular reports on field services and/or tests performed. · Travel to customer sites to rectify problems when/if necessary Work with the customer's staff to train and develop operations capability on Airties' products Support alpha and beta tests of new Airties products at customer sites Provide feedback to Sales, Product, and Engineering teams to improve Airties products Promote Airties products at customers and establish strong lasting customer relationships What you should ideally bring: Bachelor’s or higher degree in Network Engineering, EE or similar technical field is required 5+ years professional experience of which 2+ years of hands-on field experience in networking in a customer facing role delivering professional services is required Excellent communication, presentation and reporting skills in English is mandatory. This job requires extensive oral communication skills to deal with customer’s teams, and written communication skills to produce reports and technical notes to customers. Demonstration of oral and written English proficiency will be required during application Strong understanding of network protocols/standards: TCP, UDP, IP, Ethernet, Wi-Fi protocols, and IEEE 802.11 standards is mandatory Knowledge of network tools like Wireshark, tcpdump, Iperf, etc. · Shell/Phyton scripting knowledge is a plus General understanding of AWS and similar cloud technologies along with Tableau, Databricks and Grafana Linux and very comfortable with CLI in various environments Expert in remote access tools and applications: Telnet / SSH / SCP / TFTP / Serial Console Experience with broadband, IPTV, and streaming video technologies is big plus Experience with Customer Premise Equipment devices, residential gateways, set top boxes is required. Familiarity with CPE management software solutions is a plus Ability to travel within short notice is required. This position requires international travel up to 50% of work time. Airties has a zero tolerance to discrimination policy. In this regard, during the course of the evaluation of your job application and during all your employment relation, if any, all discriminatory factors such as race, sex, sexual orientation, social gender definitions/roles, color, national or social background, ethnicity, religion, age, disablement, political opinion or any status that is protected under law shall be totally disregarded. *By applying to this job opening, you agree, acknowledge and consent to the transfer of your personal data by Airties to outside of Turkey; in particular to its subsidiaries. *By applying to this job opening, you agree, acknowledge and consent to the transfer of your personal data by Airties to its headquarters established in Turkey. Show more Show less

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! We are now looking for highly driven and innovative ASIC / Hardware Engineers. We are looking for bright engineers across our hardware engineering groups to help us Architect, Design and verify our next generation GPUs, CPU and SoCs meant to accelerate the performance of Data Center, Machine Learning, Autonomous Driving, Ray Tracing and many more exciting applications. You will get to work on high performance GPU / SOC/ CPU across Memory sub-systems, Graphic processing units, NOC based Interconnect Fabric, High speed IO's etc. What You'll Be Doing Work on hardware models of different levels of extraction, including performance models, RTL test benches and emulators to find performance bottlenecks in the system. Work closely with the architecture and design teams to explore architecture trade-offs related to system performance, area, and power consumption. Understand key performance use cases or the product. Develop workloads and test suites targeting graphics, machine learning, automotive, video, compute vision applications running on our products. You will be responsible to make architectural trade-offs based on feature/performance/power requirements, analyse system implications, come up with the micro-architecture, implement RTL, drive the verification, close timing, and support silicon validation. Developing test plans, tests and verification infrastructure for complex IP's/sub-system/SOC's. Creating verification environment using UVM methodology and reusable bus functional models, monitors, checkers and scoreboards. Driving functional coverage driven verification closure. Develop and enhance timing analysis/signoff work-flow from frontend (pre-layout) to backend (post-layout) at both chip and block level. Develop custom timing scripts using tcl/primetime for clock skew analysis, special circuits such as clock dividers, core logic IO macros interfaces such as PCI-E, Frame-Buffer/Memory, HDMI, etc. Chip level Integration, physically partitioning and floor planning along with Physical Verification and EM IR Drop You will be responsible for the design and implementation of state-of-the-art designs in test access mechanisms, IO BIST, memory BIST and scan compression. In addition, you will help develop and deploy DFT methodologies for our next generation products. Be apart of innovation to strive improve the quality of DFT methods. Work with architects, designers and post-silicon teams. What We Need To See BTech/MTech with 2+ years of experience in micro-architecture, RTL development of complex designs. Possess strong digital design fundamentals. Preferably have a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor planning, ECO, bring up and lab debug is a prerequisite for this role. If you have experience in at least a few of the following skills, we will have an excellent match for our needs: GPU / CPU / SOC Performance verification and analysis. CPU, Memory controller, Bus Interconnect, Cache coherency IP / SOC Design, Micro-architecture across High Speed IO controller (UFS/PCIE/ XUSB), Network on Chip / 10G Ethernet MAC and (or) Switch IP / SOC Graphics Processing Unit (GPU Design & Verification) BOOT and Power management features for complex SOC’s FPGA Prototype with prior experience in HAP Good debugging and analytical skills. Good interpersonal skills and ability to work as an excellent teammate Excellent communication skills to collaborate with cross-cultural teams and work in a matrix organization With highly competitive salaries and a comprehensive benefits package, NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people in the world working for us. If you're creative and independent, with a genuine real passion for technology, we want to hear from you. JR1978791 Show more Show less

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As verification engineer candidate will be responsible to manage UFS/Ethernet/PCIe/high speed IP verification at SOC level. Responsibilities : Understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design. Responsible to implement and analyze system Verilog assertion and coverage(code, toggle, functional) . Work alongside other members of the verification team to analyze, develop and execute verification test cases and able to provide relevant solution to issue. Collaborate with architects, designers, and pre and post silicon verification teams to accomplish your tasks. Adhere to quality standards and good test and verification practices. B.E/B. Tech/M.E/M. Tech in electronic with 2+ year experience in verification domain. Prior work experience on IP level or Soc level. Good understanding of process Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Job Area: Engineering Group, Engineering Group > Software Engineering General Summary: At least 3-6 years of relevant hands-on technical experience in WLAN/Linux driver development with a record of strong managerial and individual technical achievement Strong programming skills in C Must have hands on experience working in the Linux kernel & Linux kernel device drivers Must have hands on experience working in networking components in the Linux Kernel Must have hands on experience in Networking driver development; Ethernet and Wireless LAN driver development is preferred Must have hands on experience in solving complex system issues with good problem solving skills Should be able to work in aggressive, high pressure environment Should be able to interact with team members and other teams across geos to clearly identify the requirements and plan within resource constraints WLAN driver experience is an added advantage Able to travel aboard Excellent communication skills Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Software Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 1+ year of Software Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field. 2+ years of academic or work experience with Programming Language such as C, C++, Java, Python, etc. Experience- 3-6 years of relevant hands-on technical experience

Job Area: Engineering Group, Engineering Group > Software Engineering General Summary: 3+ yrs in SW Engineering life cycle or related work experience Strong SW development skills and experience iin SW engineering roles that covers SW design, architecture, development and test. Strong technology focus and experience in networking technology areas that include WLAN, Ethernet, Bridging and Routing. Good understanding of requirements for products and features, Strong understanding SW architecture and real time embedded system design with Linux Operating System Decisive and ability to quickly identify problems & make decisions to solve them. Strong interpersonal and communication skills Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Software Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 1+ year of Software Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field. 2+ years of academic or work experience with Programming Language such as C, C++, Java, Python, etc. Experience working with cross geo teams in US and worldwide Good theoretical understanding of software architectures in networking, WLAN, data path functions. Exposure to Mesh technologies in Wi-Fi Forward looking attitude, analyse upcoming trends in Wi-Fi and Networking

Job Area: Engineering Group, Engineering Group > Software Engineering General Summary: Minimum 15 yrs in SW Engineering life cycle. Minimum 10 yrs in SW engineering roles that covers SW development and test. Strong technology focus and experience in networking technology areas that include WLAN, Ethernet, Bridging and Routing. Strong understanding SW architecture and real time embedded system design with Linux Operating System Experience in detailed planning, reporting, defining and managing engineering / technology metrics Decisive and ability to quickly identify problems & make decisions to solve them. Strong interpersonal and communication skills Ownership of commercialization of the key Wi-Fi access point products Technical product owner of the releases responsible of driving all technology areas to deliver world class AP and Wi-Fi Routers Primary technology and commercialization interface with product management and engineering teams End to End ownership to drive programs from start to the post launch in the field. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 6+ years of Software Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 5+ years of Software Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 4+ years of Software Engineering or related work experience. 3+ years of work experience with Programming Language such as C, C++, Java, Python, etc. Experience in managing programs & meets required program specifications with required quality, content & cost Global program management experience across geos Working with cross geo teams in US and China Customer interactions and Product Marketing interfacing experience

Job Area: Engineering Group, Engineering Group > Software Engineering General Summary: As an Engineer in the EasyMesh Group, you will be part of a team that implements functional aspects of EzMesh features in QCOM WiFi Chipsets, that will work in tandem with device drivers running on the host processors and its commercialization. You would be involved in implementation of standard features, its testing and commercialization to different ODMs. You will be working on cutting edge WiFi technologies, solving challenging performance issues from some of the leading WiFi ODMs & OEMs across the globe on their sometimes-high pressure & tough timelines. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field. Skills/Experience Overall experience of at least 1-3 years which includes minimum 1-2 years of C programming At least 1-2 years of relevant hands-on technical experience in WLAN standards with a record of strong individual technical achievement - Strong programming skills in C - Must have hands on working experience working on real-time embedded systems - Experience in working on Firmware in small memory footprint processors is a BIG plus - Hands on experience in Networking driver development, Ethernet and Wireless LAN driver development preferred - Excellent verbal and written communication skills - Experience in EasyMesh / SON technology is a BIG plus. Need to be a team player

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: This position is for RTL designer role in DSP processor team. The position involves in-depth understanding of the ASIC design flow from RTL to GDS2 and the challenges posed by advanced technologies. The successful candidate will possess detailed understanding of RTL design, synthesis, static timing analysis, formal verification, PLDRC, clock domain crossing, and low power techniques. Knowledge and experience of microprocessor integration is a definite advantage. Skills/Experience Must have 10 to 15 years of practical experience with details of RTL development (VHDL and/or Verilog) including:functional and structural RTL design, design partitioning,simulation and regression, collaboration with design verification team. Must have good familiarity with latest RTL languages and tools, includingsimulation systems (e.g. Modelsim, VCS), synthesis tools (e.g. Design Compile), static timing tools (e.g. Prime Time), Linting tools, CDC tools, UPF, code coverage, System Verilog Assertion, etc. Experience with the following area is highly desirable Strong processor architecture knowledge Microarchitecture implementation Microprocessor integration Low power design Responsibilities Develop RTL for multiple logic blocks of a DSP core Run various frontend tools to check for linting, clock domain crossing, synthesis, etc. Work with physical design team on design constrain and timing closure Work with power team on power optimization Work with verification team to collaborate on test plan, coverage plan, and coverage closure Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: s verification engineer candidate will be responsible to manage UFS/Ethernet/PCIe/high speed IP verification at one or more SoC (System On Chip) during project work. Responsibilities Understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design. Responsible to implement and analyze system Verilog assertion and coverage(code, toggle, functional) . Work alongside other members of the verification team to analyze, develop and execute verification test cases and able to provide relevant solution to issue. Collaborate with architects, designers, and pre and post silicon verification teams to accomplish your tasks. Adhere to quality standards and good test and verification practices. B.E/B. Tech/M.E/M. Tech in electronics with 5+ year experience in verification domain. Prior work experience on IP level or Soc level. Prior work on UFS (Universal Flash Storage),Ethernet and PCIe Protocol is desirable. Good understanding of processor based Soc level verification which includes native ,Verilog ,system Verilog and UVM mix environment. Hand on experience with verification tools such as VCS, waveform analyzer and third party VIP integration (such as Synopsys VIPs). Hands on experience in UVM. C/C++ ,System Verilog verification language. Good understanding of AXI-AMBA protocol variants. Can work with scripting language (shell, Makefile, Perl ) Strong understanding of design concepts and ASIC flow. Good problem solving , analytical and debugging skill is must. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Skills/Experience : 6 months - 2 years of strong experience in digital front end ASIC design verification Bachelors or Masters Degree in Engineering in Electronics, VLSI, Communications or related field. We are looking for a highly motivated and talented RTL verification engineer to join our team to work on the next generation complex cores used in High End Modem/Mobile chips. In this role, a successful incumbent would- Develop verification environment and testbench components such as BFM and checkers. Develop comprehensive test plan for unit level verification of IP/Module features and implement test cases. Verify design in unit level environment using directed and constrained random testing, assertion-based verification, formal analysis, and functional verification. Write functional cover-groups and cover-points for coverage closure. Perform RTL code coverage, assertion coverage, functional coverage and gate level simulations. Have expertise in verifying designs at system level and block level using constrained random verification. Operate at Expert level in System Verilog and UVM based verification. Expertise in coding SV Testbench, drivers, monitors, scoreboards, checkers - Strong and independent design debugging capability. Understanding of AHB, AXI and other bus protocols, digital design and system architecture - Understanding of TCP/IP Packet Processing Algorithms like Filtering, Routing, NAT, Decipher, Checksum, Ethernet Bridging, Tunneling is a Plus. Should possess good communication skills to ensure effective interaction with Engineering Management and team members. Should be self-motivated with good teamwork attitude and need to function with minimal guidance or supervision Responsibilities : Work in close coordination with Systems, Design, SoC team , SW team, Validation & DFT teams to get the goals completed. Developing the Verification Strategy, Testbench architecture and implementing the design verification plan and tests using SV/UVM/C. HW verification using Cadence and Synopsys simulator tools, SV/UVM based TB development, Regression analysis, bug-triage. Formal Verification using Jasper, VCF etc. Power Aware Verification on RTL and DC/PD Gate lebel Netlist. Conducting High-/Mid-/Low- level verification reviews, coverage closure and sign-off on block and Sub-system testing. Assisting SOC team with IP Integration testing at SOC level. Post-Silicon Debugs in close collaboration with Design, Validation and SW teams. Self-Motivated to Execute the defined tasks almost independently with minimal guidance Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.