124 Esd Jobs - Page 5

• Drive Area estimation, Floor Planning, Placement, Routing, Power planning, Verification, EMIR, ESD-LUP Verification & Tape out. • Understanding of low parasitic, high frequency design techniques. • Finfet process & Lower nodes; 2nm/3nm/5nm/7nm Required Candidate profile • Exp with Cadence (Virtuoso), Synopsys (CC), Calibre & ICV verification tools like LVS, DRC, Extraction. • Debugging/fixing LVS/DRC errors • Experience with EMIR, PERC tools. • Skill/TCL scripting.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Overview In this highly cross functional role, you will be part of the Global Design Enablement team responsible for the physical verification aspects of PDK development. You will conceptualize, develop, maintain and improve the Physical Verification flows. The role requires you to work on flow and rule deck development for various technology nodes utilizing the state of the art tools. You will be collaborating with the Custom Digital/Analog/Mixed Signal/RF, Physical design (PD) and Chip integration teams to understand their requirements and challenges and enabling flows to meets their needs. This role requires a thorough understanding of Design Rule Checks (DRC), Layout Versus Schematic (LVS) and Layout and Programmable ERC, implementing the rules from scratch and/or modify the existing ones . Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Minimum Qualification Minimum 5 years experience in a hands-on PDK role Expertise in Calibre/ICV runset coding for DRC/LVS/ERC/PERC/ESD/Latch-up/Antenna". As a member of the Physical Verification CAD team, you will maintain and improve all aspects of physical verification flow and methodology Code custom checks such as Layout/Programmable ERCs, addition of custom devices in LVS, implementation of custom design rules(DRCs), etc to meet the needs of the design teams You will need to have a deep understanding of design rule checks (DRC) and layout versus schematic (LVS) runsets, writing from scratch and/or modify existing ones. Proficiency in integration and tech setup of Calibre LVS with StarRC/QRC and other Extraction tools Support the design teams with solving their PV challenges to facilitate the IP release and Chip tapeouts Collaborate with tool vendor and foundries for tools and flow improvements Knowledge of deep sub-micron FINFET, Planar, SOI and PMIC process technologies and mask layout design Proficiency in one or more of the programming/scripting languages- , Python, Unix, Perl, and TCL. Good communication skills and ability to work collaboratively in a team environment Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

We Are: At Synopsys, we drive the innovations that shape the way we live and connect Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: An experienced and passionate Analog Design Engineer with 1-3 years of experience in the field You have a strong background in CMOS processes and deep submicron process technologies You understand the intricacies of CMOS circuit design and layout methodology, and you have a basic understanding of analog/mixed signal circuitry Familiarity with ESD concepts is a plus You are knowledgeable about ASIC design flow and JEDEC requirements for DDR interfaces and standards You excel at executing circuit design tasks with a focus on quality and efficiency Your communication skills are excellent, enabling you to interact effectively with internal development teams, What Youll Be Doing: Designing DDR/HBM Memory Interface I/O circuits and layouts, including GPIO and special I/Os, Collaborating with the DDR/HBM PHY team, package engineers, and system engineers to meet design specifications, Ensuring adherence to best practices in circuit design and layout methodology, Conducting thorough design reviews and contributing to the continuous improvement of design processes, Staying updated with the latest advancements in analog design technologies and methodologies, Documenting design processes and providing support for design validation and testing, The Impact You Will Have: Enhancing the performance and reliability of our analog and mixed-signal circuits, Contributing to the development of high-performance DDR/HBM Memory Interfaces, Supporting the overall success of our chip design and IP integration projects, Driving innovation in analog design methodologies and processes, Ensuring our products meet the highest standards of quality and efficiency, Helping Synopsys maintain its leadership position in the semiconductor industry, What Youll Need: Bachelor's or Master's degree in Electronics or Electrical Engineering, 1-3 years of experience in CMOS processes and deep submicron technologies, Proficiency in CMOS circuit design and layout methodology, Basic understanding of analog/mixed signal circuitry, Familiarity with ASIC design flow and JEDEC requirements for DDR interfaces, Who You Are: A detail-oriented engineer with a passion for analog design, An effective communicator who collaborates well with cross-functional teams, A problem-solver who can analyze and address design challenges efficiently, A continuous learner who stays updated with industry trends and advancements, A team player who contributes to the overall success of the project, The Team Youll Be A Part Of: You'll join a dynamic and innovative team of engineers focused on advancing our analog design capabilities Our team is dedicated to pushing the boundaries of technology and delivering cutting-edge solutions for the semiconductor industry We value collaboration, creativity, and a commitment to excellence in everything we do, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process,

Senior Instrumentation Engineer - CHE00RX Company Worley Primary Location IND-TN-Chennai Job Instrumentation and Controls Schedule Full-time Employment Type Employee Job Level Experienced Job Posting Apr 23, 2025 Unposting Date May 29, 2025 Reporting Manager Title Department Manager Building on our past. Ready for the future Worley is a global professional services company of energy, chemicals and resources experts. We partner with customers to deliver projects and create value over the life of their assets. Were bridging two worlds, moving towards more sustainable energy sources, while helping to provide the energy, chemicals and resources needed now. The Role As a Senior Instrumentation Engineer with Worley, you will work closely with our existing team to deliver projects for our clients while continuing to develop your skills and experience etc. To be considered for this role it is envisaged you will possess the following attributes: Preparation of Instrumentation engineering deliverables including Specifications, Instrument Datasheets, Logic Diagrams etc. Deliver instrumentation & controls specific design and drafting services that meet Worley the customer's and applicable statutory and regulatory requirements. Knowledge of SPI / AVEVA Able to prepare instrument datasheets, Index, IO list and other SPI deliverables. Able guide the designers for modelling activity, having good communication skills. Carryout sizing calculations for Control Valves, Flow Meters, Pneumatic & Hydraulic Power Systems Instrument cable voltage drop & Intrinsically Safe Circuit Calculations Preparation of Fire & Gas Detectors & Alarm Device Datasheets Inter-disciplinary document comments and reviews Provide inputs and review of engineering drawings including Instrument Location Plans, Cable & JB Schedules, Cable Routing Layouts, Instrument Installation Details, Process / Pneumatic Hook-Ups, Interconnection Diagrams, Loop Diagrams, Fieldbus Segment Diagrams, Interconnection Diagrams, Instrument Loop Diagrams Liaison with the Instrument Designers Produce Systems Vendors modifications Scopes of Work documents. Carryout onshore and offshore site surveys as required. Attend interface meetings with Clients and Vendors to progress design scopes. Review Instrumentation and Control Systems Vendors offers, prepare Vendor Technical Clarifications, and prepare Technical Bid Evaluation reports. About You To be considered for this role it is envisaged you will possess the following attributes: Minimum 12+ years experience in detailed engineering and design of Instrumentation & Control works for Oil & Gas projects in similar position Fully familiar with relevant international codes, standards and recommended practices such as ISA, NEC, NFPA, BS API, IEC,etc Should have hands on experience in INTOOLS (SPI) software. Working knowledge of AVEVA instrumentation. The candidates should have hands on experience of multi-disciplinary projects in Concept, FEED and Detail Engineering of field Instrumentation, Control & Monitoring and Safety Shutdown Systems, including DCS, ESD and F&G, in the onshore / offshore O&G and petrochemical environment. Developing technical and practical instrumentation & controls design and drafting skills in the same or similar industry. Developing skills in design software. Competent use of relevant software such as MS Office Suite Degree in Electrical, Electronics or Instrumentation & Control Engineering or equivalent Moving forward together Were committed to building a diverse, inclusive and respectful workplace where everyone feels they belong, can bring themselves, and are heard. We provide equal employment opportunities to all qualified applicants and employees without regard to age, race, creed, color, religion, sex, national origin, ancestry, disability status, veteran status, sexual orientation, gender identity or expression, genetic information, marital status, citizenship status or any other basis as protected by law. We want our people to be energized and empowered to drive sustainable impact. So, our focus is on a values-inspired culture that unlocks brilliance through belonging, connection and innovation. And we're not just talking about it; we're doing it. We're reskilling our people, leveraging transferable skills, and supporting the transition of our workforce to become experts in today's low carbon energy infrastructure and technology. Whatever your ambition, theres a path for you here. And theres no barrier to your potential career success. Join us to broaden your horizons, explore diverse opportunities, and be part of delivering sustainable change.

exp in the field of process control & automation. DCS Design exp in Engineering Industry. • Analyse customer inputs and understand requirements Design Specifications, P&IDs, Control Narratives, IO list, Instrument Index, Operating Philosophies etc.

www.Sevyamultimedia.com Layout Lead About Us We are a technology consulting company delivering best-in class Chip Design Services. Founded in 2008, we partner with top semiconductor companies in building a connected, safer tomorrow. With over 40+ tapeouts and expertise spanning the breadth of chip design, we offer a wide variety of Semiconductor skills Approach We support a mix of engagement models to support diverse client requirements. Engagement Models Turnkey (SoW) Engagement Staff Augmentation (T&M) Offshore Design Center Key Enablers Hands on Leadership Proven Industry Experts TSMC DCA Parternship Collaboration with Academia Message About the job Analog Layout Design Lead with 7+ years of relevant work experience You will be doing Analog Layout in advanced process technologies, serving global Semiconductor product MNC clients. What you get: Inducted in the advanced Analog VLSI projects Get an opportunity to work with clients that are world-class VLSI MNCs Skills: Hands-on knowhow in analog and mixed-signal layout techniques and experience with Cadence Layout tools (Virtuoso) and Mentor Graphics verification tools (Calibre) Experience in Custom Analog Layout (one or more) of I/O, Amplifiers/OPAMP circuits, ADCs/DACs, LDOs, Bandgaps & Bias Circuits, Temperature Sensor, Oscillators Physical Verification ( LVS, DRC, ERC, ANT with Calibre) Ability to recognize and correct problematic circuit and layout structures Knowledge of relevant device physics, matching techniques, ESD/Latchup mitigation techniques, circuit parasitic extraction & reduction, VXL compliance etc., is expected Ability to closely and independently work with Analog Designers to solve performance and area challenges Traits: Quick learner with excellent interpersonal, verbal/written communication, problem-solving, and decision-making skills Adaptable, Flexible, Global Approach/Synthesis, Creative Willing to work on customer site for deployment and support Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

www.Sevyamultimedia.com Layout Senior Manager/ Manager About Us We are a technology consulting company delivering best-in class Chip Design Services. Founded in 2008, we partner with top semiconductor companies in building a connected, safer tomorrow. With over 40+ tapeouts and expertise spanning the breadth of chip design, we offer a wide variety of Semiconductor skills Analog IP Design Foundation - OpAmp, Bandgap IOs - GPIO, I2C, LVDS Clocking - PLL Power - LDO PDK, Design Automation DRC/LVS/Extraction Rule deck Development PCell Development Automation Tools in Perl, Python, GoLang Approach We support a mix of engagement models to support diverse client requirements. Engagement Models Turnkey (SoW) Engagement Staff Augmentation (T&M) Offshore Design Center Key Enablers Hands on Leadership Proven Industry Experts TSMC DCA Parternship Collaboration with Academia Location: Hyderabad #### **Job Summary:** We are seeking an experienced and dynamic Layout Design Manager to lead our layout design team. The ideal candidate will have a strong background in analog-on-top chip layout for devices with high-speed IO and analog components, as well as experience in dealing with ESD/latch-up issues, bump matrix design, RDL routing, power distribution, and critical signal planning. This role requires excellent leadership skills, the ability to manage complex design projects, and a strong technical background in layout design. #### **Key Responsibilities:** - **Team Leadership:** - Lead, mentor, and manage a team of layout design engineers. - Foster a collaborative and innovative team environment. - Develop team skills through training and professional development initiatives. - **Project Management:** - Plan and estimate layout design tasks, resources, and schedules. - Track and report on project progress, ensuring timely delivery of milestones. - Coordinate with cross-functional teams, including design, verification, and packaging, to align layout design activities with project goals. - **Analog-on-Top Layout Design:** - Oversee the layout design of analog-on-top chips with high-speed IO and analog components. - Ensure designs meet performance, power, area, and manufacturability requirements. - Optimize layout for ESD and latch-up prevention, signal integrity, and noise immunity. - **Bump Matrix and RDL Routing:** - Manage the design of bump matrix and redistribution layer (RDL) routing for advanced packaging. - Ensure efficient power distribution and critical signal planning. - **ESD/Latch-Up and Power Distribution:** - Address and resolve ESD and latch-up issues in layout designs. - Design robust power distribution networks to ensure reliable chip operation. - **Critical Signal Planning:** - Plan and implement critical signal routing to minimize interference and maximize performance. - Optimize layout for signal integrity and timing closure. - **Hiring and Training:** - Participate in the hiring process to recruit top talent for the layout design team. - Provide training and mentorship to new hires and junior engineers. - **Continuous Improvement:** - Stay updated with the latest industry trends, tools, and methodologies in layout design. - Drive continuous improvement initiatives to enhance design processes and methodologies. - Implement best practices for layout design and contribute to the development of standards and processes. #### **Qualifications:** - **Education:** - Bachelors or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. - **Experience:** - 10-15 years of experience in layout design, with at least 3 years in a managerial or leadership role. - Proven experience in analog-on-top chip layout for high-speed IO and analog devices. - **Technical Skills:** - Extensive experience with ESD and latch-up prevention techniques. - Proficiency in bump matrix design and RDL routing. - Strong knowledge of power distribution networks and critical signal planning. - Familiarity with CAD tools (e.g., Cadence Virtuoso, Mentor Graphics) for layout design. - Experience with physical verification (DRC, LVS) and parasitic extraction. - **Soft Skills:** - Excellent leadership and team management abilities. - Strong problem-solving and analytical skills. - Effective communication and interpersonal skills. - Ability to work in a fast-paced, dynamic environment and manage multiple projects simultaneously. #### **Preferred Qualifications:** - Experience with advanced node technologies (e.g., FinFET, SOI). - Knowledge of reliability testing and failure analysis for analog and high-speed IO circuits. - Familiarity with scripting languages (e.g., Python, Perl) for automation. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

www.Sevyamultimedia.com Layout Lead About Us We are a technology consulting company delivering best-in class Chip Design Services. Founded in 2008, we partner with top semiconductor companies in building a connected, safer tomorrow. With over 40+ tapeouts and expertise spanning the breadth of chip design, we offer a wide variety of Semiconductor skills Approach We support a mix of engagement models to support diverse client requirements. Engagement Models Turnkey (SoW) Engagement Staff Augmentation (T&M) Offshore Design Center Key Enablers Hands on Leadership Proven Industry Experts TSMC DCA Parternship Collaboration with Academia Message About the job Analog Layout Design engineer with 3-7+ years of relevant work experience You will be doing Analog Layout in advanced process technologies, serving global Semiconductor product MNC clients. What you get: Inducted in the advanced Analog VLSI projects Get an opportunity to work with clients that are world-class VLSI MNCs Skills: Hands-on knowhow in analog and mixed-signal layout techniques and experience with Cadence Layout tools (Virtuoso) and Mentor Graphics verification tools (Calibre) Experience in Custom Analog Layout (one or more) of I/O, Amplifiers/OPAMP circuits, ADCs/DACs, LDOs, Bandgaps & Bias Circuits, Temperature Sensor, Oscillators Physical Verification ( LVS, DRC, ERC, ANT with Calibre) Ability to recognize and correct problematic circuit and layout structures Knowledge of relevant device physics, matching techniques, ESD/Latchup mitigation techniques, circuit parasitic extraction & reduction, VXL compliance etc., is expected Ability to closely and independently work with Analog Designers to solve performance and area challenges Traits: Quick learner with excellent interpersonal, verbal/written communication, problem-solving, and decision-making skills Adaptable, Flexible, Global Approach/Synthesis, Creative Willing to work on customer site for deployment and support Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Job Responsibilities 1. Schneider / Siemens PLCs and SCADA experience in Oil & Gas, Petrochemical and Utility (Water & Power) Industries. 2. Should have worked on PCS7, S7 400 H PLC OR M580 Systems in Redundant (Hot standby) Configuration with Server-client architecture of SCADA System. 3. Understanding of field instrumentation and its interface with PLC, RTU over communication bus. 4. Complete understanding of the engineering documents associated with instrumentation such as: P&IDs, loop diagrams, specification sheets, writing diagrams, ladder logic, logic diagrams, installation detail drawings, etc. 5. Complete understanding of field construction, sequence of events, how to track progress, how to verify proper installation, and control loop checking 6. Participate in developing the functional description of the automation solution (e.g., control scheme, alarms, HMI, reports) using rules established in the definition stage in order to develop and program. 7. Responsible for FAT and SAT.

Were Hiring! | Technical Sales Engineer SMT / PCBA Equipment Location: Chennai / Bangalore, India Company: EWG Apply at: carrerewglobal@gmail.com Position Overview: We are looking for an experienced and results-driven Technical Sales Engineer specializing in SMT / PCBA equipment and consumables. This is a full-time, on-site position based in Chennai / Bangalore. As part of our growing sales team, you will play a key role in understanding customer requirements, providing technical consultation, and driving sales of high-performance SMT solutions. Key Responsibilities: Drive sales of SMT/PCBA equipment and consumables Provide technical support and product demonstrations to clients Develop and maintain strong customer relationships Understand customer pain points and recommend appropriate solutions Collaborate with the internal technical team to deliver exceptional customer service Qualifications: 2 to 4 years of experience in SMT / PCBA industry (mandatory) Strong technical knowledge in SMT equipment, PCB assembly processes Excellent communication and interpersonal skills Proven track record in technical sales and customer support Diploma Engineering / Bachelor's degree in Engineering or a related technical field Problem-solving mindset with a customer-first approach Why Join Us? Work with a company at the forefront of ECO-Friendly electronics manufacturing. Be part of a technically strong and supportive team Opportunity to grow with a rapidly expanding business Ready to take the next step in your career? Send your resume to carrerewglobal@gmail.com Lets build the future of electronics manufacturing together!

Responsibility: Early involved in the NPI process with project team to identify the quality risk and drive process to close quality issues and complete QCP, IPQC FAI before MP. Work with project teams to understand customer quality requirements and set up product & process quality criteria with BPL factory. To monitor the product quality control system and product quality at BPL side to fulfill Company Devices requirement. 1. Drive continuous improvement initiatives for both product and system quality at BPL and monitor improvement actions have implemented in place.2. Chase for collecting/ analyzing the FOR (quality yield rate) and leading functional team to take improvement actions quickly to make sure meet the quality target.3. Co-work with China team to judge and solve materials issues at IQC and Process. 4. Take responsibility for OQC/OBA inspection & test maintenance and issues solving, ensure product out-going quality level is under control. 5. Lead BPL to implement inner audit regularly, including 5S, FAI, ESD, Process, etc. Follow up the company quality KPI and reduce the non-quality cost. Review and share weekly/ monthly KPI reports with customers. Coordinate customer audits at BPL and follow improvement actions. Co-work with customer support engineers to solve customer complaints. Requirement University degree in Electrical or Engineering background Minimum 10 years working experience. EMS factory quality experience and know PCBA/ SMT and assembly well. Quality tools requirement: Familiar with analytical tools, such as FMEA, process control plan and SPCBasic inspection techniques. Familiar with MSA, ESD, QCP and Factory audit.Know well about the ISO quality systems. Good communication skill and fluent in English. Share your updated CV to profiles@intellisearchonline.net

Roles & responsibilities Well knowledge in Samsung and Panasonic mounters Well knowledge in ICT and program downloaders Well knowledge in Parmi & Koyung AOI Well knowledge in SP and SPI machines Well knowledge in SMT process Well knowledge in Electrical & Electronics troubleshooting Knowledge in Break down Analysis documents Basic knowledge of EOL Well knowledge in Soldering equipments Well knowledge in ESD Preferred candidate profile BE/Diploma in EEE or ECE required 5-7 yrs of relevant experience required Transport available from Avadi, Tiruvallur, Porur, Ponnamallee, Sriperumbudur.

Job Overview : We are seeking an exceptional Physical Verification Engineer to take a key role in oursemiconductor design team. As a Block/Fullchip/Partition Physical Verification Engineer , you willResponsible for development and implementation of cutting-edge physical verification methodologiesand flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensurethe successful delivery of high-quality designs Responsibilities : Drive physical verification DRC, Antenna, LVS, ERC at cutting edge FinFET technology nodesfor various foundries. Physical verification of a complex SOC/ Cores/ Blocks DRC, LVS, ERC, ESD, DFM, Tape out. Work hands-on to solve critical design and execution issues related to physical verificationand sign-off. Own physical verification and sign-off flows, methodologies and execution of SoC/cores. Good hands on Calibre, Virtuoso etc. Requirements: Bachelors or Masters degree in Electrical Engineering or Electronics & Communications. Proficiency in industry-standard EDA tools from Cadence, Synopsys and Mentor Graphics. Strong scripting skills using TCL, Python, or Perl for design automation and tool customization. Expertise in physical verification of Block/Partition/ Full-chip-level DRC, Experience and understanding of all phases of the IC design process from RTL-GDS2. LVS, ERC, DFM Tape out process on cutting edge nodes, Preferably worked on 3nm/5nm/7nm/12nm/14nm/16nm nodes at the major foundries Experience in debugging LVS issues at chip-level/block level with complex analog-mixed signal IPs Experience with design using low-power implementation (level-shifters, isolation cells, power domain/islands, substrate isolation etc.) Experience in physical verification of I/O Ring, corner cells, seal ring, RDL routing, bumps and other full-chip components Good understanding of CMOS/FinFET process and circuit design, base layer related DRCs, ERC rules, latch-up etc. Experience with ERC rules and ESD rules has an added advantage Outstanding communication and interpersonal skills, with the ability to collaborate effectively in a team environment. Proven ability to Engineer and mentor junior engineers, fostering their professional growth and development. Preferred qualifications: Experience with advanced process nodes 3nm, 5nm, 7nm, 10nm including knowledge of FinFET technology. Proven track record with multiple successful final production tape-outs Proven ability to independently deliver results and be able to work hands-on as and guide/help peers to deliver their tasks Be able to work under limited supervision and take complete accountability. Excellent written and verbal communication skills Knowledge on Handling various custom IP such as PLL, Divider, Serdes, ADC, DAC, GPIO, HSIO for PD integration and Physical verification challenges.

Should have experience on Mixed Signal Design, Analog Circuit Design and Digital Circuit Design Should have experience in working on complete Product Development Life Cycle Should have a strong understanding of Signal and power Integrity phenomena and relevant tools. Should have knowledge of working on micro controllers, microprocessors and FPGAs from various industry manufacturers like TI, STM, Qualcomm, Xilinx, Lattice and others. Should have knowledge of communication protocols like SPI, I2C, USB, UART, CAN, Ethernet, Wi-Fi, RS485 a few to mention. Should possess excellent knowledge of various power regulators like Switching and LDOs. Should have experience of Schematic Design in Altium and Orcad Should have reviewed the layout designs and guided PCB designers for an effective component placement and routing for various designs. Should have worked on Multi-layer board design with minimum 6 layers. Understanding of the layer stack-up definition and its understanding is desired. Should have knowledge of using various electronic tools and instruments like Oscilloscopes, multi meters and others. Should have excellent debugging skills with analytical reasoning. Should have experience in making the designs meet various compliance standards related to safety, ESD, EMI/EMC. Excellent interpersonal, written and verbal communications skills; flexible, self-directed and able to work in a team environment. Knowledge of Change/Configuration Management and ECN processes is a Plus Should possess excellent knowledge of various power regulators like Switching and LDOs. AC to DC Power Supply Design and debugging Should have strong knowledge in working on various motors like BLDC, stepper, etc. Should have strong knowledge of working on Encoders, motor drive

JD for Clean room Environment maintenance Technician Job Title: Clean room Environment monitoring Department: Cleanroom Operations / Quality Assurance / Facilities Location: Semiconductor Fabrication Facility (FAB) Reports To: Cleanroom Environmental Monitoring Engineer / Facilities Head Job Summary: The Cleanroom Particle Count Technician is responsible for performing daily Temperature, Rh, airborne particulate monitoring in classified cleanroom environments (ISO Class 5 to ISO Class 8) in a semiconductor manufacturing facility. The technician ensures strict compliance with ISO 14644 standards and internal protocols to protect wafer integrity and yield. Key Responsibilities: Conduct daily Temperature, Rh, airborne particle count measurements in cleanroom zones using calibrated laser particle counters . Ensure cleanroom conditions meet ISO Class 58 standards applicable to semiconductor manufacturing. Perform scheduled, unscheduled, and event-driven particle monitoring as per SOPs. Operate and maintain particle counters (e.g., TSI, Lighthouse, Met One), isokinetic probes, and supporting software. Accurately record, review, and trend data to detect deviations or contamination sources. Work with process engineers and facilities team to identify and resolve air quality issues . Report out-of-spec results immediately and support corrective action activities. Maintain logs and ensure all monitoring activities are properly documented and audit-ready. Participate in FAB requalification, tool hook-up validation , and HEPA filter testing support. Assist during internal audits and external inspections (ISO, ESD, EHS, customer audits). Ensure compliance with ESD protocols , cleanroom gowning , and movement procedures. Required Qualifications: Diploma / B.Sc / B.E / B.Tech in Electronics, Physics, Microbiology, Environmental Engineering, or related field Minimum 5–7 years of cleanroom monitoring experience in a Pharma/ semiconductor FAB or advanced electronics manufacturing Proficient in use and maintenance of laser particle counters and ISO 14644-1 requirements Familiar with semiconductor cleanroom protocols / GMP , tool qualification , and contamination control practices Ability to interpret trends and participate in root cause analysis (RCA) Skilled in using MS Excel, logbooks, and monitoring software Preferred Skills & Certifications: ISO 14644 awareness or training certificate Familiarity with SEMICON cleanroom standards , HVAC HEPA validation , or FAB protocols Knowledge of Statistical Process Control (SPC) for environmental data ESD awareness training Knowledge of FAB zoning & airflow control systems Work Environment: Requires working in Class 5–8 cleanroom environments in full gowning suit Shift work may be required (based on FAB schedule) Physical stamina to carry particle counters and remain in cleanroom zones for extended periods

B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Engineering. Expertise in Analog Layout design Expertise in planar technology node / higher node 180 nm is mandatory Expertise in EMIR analysis, ESD, antenna and related layout solutions Knowledge of advanced technology nodes (7nm & below) Good understanding of advanced semiconductor technology process and device physics Full-custom circuit layout/verification and RC extraction experience Familiar with Cadence Virtuoso environment and various industry physical verification tools (DRC,LVS,DFM) Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan and Vietnam are the preferred work locations Preferred resources with valid regional work permit Location - Bangalore, Beijing, Taiwan, Vietnam

Job Summary We are seeking a skilled Instrumentation Engineer to join our engineering team and support projects in the Oil & Gas sector. The role involves designing, engineering, reviewing and maintaining instrumentation systems while ensuring compliance with organizational, client and industry standards. The ideal candidate will have strong technical expertise in process instrumentation, control systems and SmartPlant Instrumentation (SPI/INtools). Role & responsibilities Design & Engineering Prepare and review Instrument Indexes, DCS/ESD/PLC I/O LISTS and technical specifications. Develop and review datasheets for various instrumentation including control valves, on/off valves, safety relief valves, transmitters, gauges, level and flow instruments and switches. Ensure engineering designs meet project specifications, codes and standards. Document Review & Co-ordination Review P&IDs, Process Data Sheets (PDS), Piping Material Specifications (PMS), Plot Plans, General Arrangement (GA) drawings, and other relevant documents. Organize the preparation of the Technical Document Register (TDR) and identify document requirements for project execution. Co-ordinate Inter-Discipline Checks (IDCs) with other engineering teams to ensure integration of data inputs. Software & Tools Proficient in SmartPlant Instrumentation (SPI/INtools) including modules for Specification, Index, Wiring and Loop Drawings. Technical Scope Work with various instrumentation types including: Pressure : Gauges, transmitters, switches. Temperature : Gauges, transmitters, sensors. Level : DP type, magnetic radar, ultrasonic transmitters, gauges, switches. Valves : Control, on-off, safety, breather, relief, rupture disk. Flow meters and associated instrumentation. Compliance & Quality Uphold high standards of ethics, safety and transparency in all engineering work. Ensure all documents and deliverables align with project requirements and client expectations. Other Duties Support installation, testing and commissioning activities as required. Perform additional tasks as assigned by project or engineering management. Qualification and preferred skills. Bachelor's degree in Instrumentation Engineering, Electrical & Instrumentation, or related discipline. 5-7 years of relevant experience in the Oil & Gas, Chemical or Petrochemical industry. Proficient in SmartPlant Instrumentation (SPI/INtools) and MS Office tools. Strong understanding of international standards and industry best practices. Excellent communication, documentation and co-ordination skills. Ability to work effectively in multidisciplinary project teams. Experience with EPC projects.

Understanding of power delivery networks (PDN) and power integrity concepts Analysing and IR drop, across the power grid on multi Power domain / Voltage Area EM Analysis and current density check Power rail / PDN analysis, rail current and checks Developing and implementing techniques to reduce power consumption, such as power gating and voltage islands Perl, Python, TCL : For automation of tasks and analysis Understanding of EM and ESD (Electrostatic Discharge) requirements

Soldering Technician for Electronic Device manufacturing with a Minimum 1 year of experience. Should have worked on experience in soldering Components on PCB and wires.

Role & responsibilities • Process application engineer for Oil & Gas, Petrochemical and Process industries delivery services Engage in developing highly complex dynamic simulation process models and smart applications using Simulation and Optimization tools. • Understanding and analyzing project requirements and translating it into specifications and project deliverables. • Produce timely and high-quality project delivery. • Build and configure dynamic process and flow models for Oil & Gas Process • Run simulations for wide range of scenarios with built models. • Carry out dynamic process and control studies • Perform optimization and de-bottlenecking studies • Assist with Flow Assurance model building for Real-time production assurance systems • Responsible for executing OTS projects with project teams for end-to-end design & delivery for Refinery, Oil & Gas, Petrochemical, and other customers • Manage the development of functional and concept technical design specifications • Ensure implementation is done with respect to project standards and quality documents & final deliverable meets the functional specifications of the end user • Identify, advise, and incorporate modifications in simulation configuration. • Attend project reviews with Customer & Interface with project leads and customers for raising technical queries • Strong understanding of Refinery Process and & Critical Section. Having hands on Simulation experience in modelling Distillation columns, heat exchangers, rotating equipment, Reactors, Furnaces, Turbines etc. • Ensure completion of projects on schedule and within the allocated budget. • Drive product improvement, productivity & Selfskill enhancement. Preferred candidate profile • Bachelors degree in chemical engineering – Master’s degree is preferred • 6 - 8 years’ experience in Refinery or Petrochemical operations / process controls / process Engineering • Hands-on experience with any one of the skill set Advanced Process Control, Real-Time Optimization, Performance Monitoring and First Principal modelling • Skilled in some of modeling tools Aspen Hysys, Aspen GDOT, KBC Petrosim, Technip Spyro etc. • Skilled in Real Time Optimization applications like ROMeo • Skilled in APC application like Rockwell Pavilion, Yokogawa smoc, Honeywell RMPCT, ASPEN DMC plus. • Certified on modeling and simulation platform Aspen Plus / Hysys / Pro-II / Dynsim , etc. will be an advantage • Ability to read and interpret Process & Instrumentation Diagrams, Process Flow Diagrams, and control logics. • Strong written and verbal communication skills • Strong domain knowledge & Chemical Engineering principles and operations. • Good communication, writing& presentation skills. • Knowledge of DCS and ESD will be added advantage. • Ability to work in a team • Strong ability to maintain good working relationships with customers. Interested candidate should Email CV to- keshri.nandan@rforce.co.in Contact /Call @ 9901647971

Role & responsibilities 1) To Achieve Day/Month wise plan vs actual target 2) Ensure good 5S and operator safety in Shopfloor 3) Material management in Line 4) To control Rejection rate in line 5) Ensure ESD system in line 6) Ontime Work order Closer 7) To Reduce Downtime in shopfloor line 8) Inventory accuracy In production Store 9) SMT Process Knowlege

Role & responsibilities 1) To control Manpower management and Ensure Effective Manpower Utilization in Shop Floor 2) Managing and improving Production Capacity for customer demand to Achieve Plan vs Actual 3) Ensure Operator safety and 5S in Shop Floor 4) Inventory accuracy in Production store 5) Manufacturing Rejection rate control 6) Implement Lean, Six Sigma and Kaizen methodology to improve productivity 7) Ensure Work Order closer in ontime 8) Experience in EMS Field and Known About ESD PPE 9) To improve OEE % 10) Knowlege about ERP and MES Tracking 11) To Reduce TML and Scrap Rate 12) Maintain Production Consumables stock 13) SMT process knowlege and known about Rework process

: To work independently on block/IP levels analog layout design from schematic. Estimating the Area, Optimizing Floorplan, Routing and Verifications. Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 5,7,10, 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence Virtuoso Editor & Calibre RVE Good interpersonal skills and critical thinking abilities to resolve the issue technically, and professionally. Key Responsibilities: Independently execute block/IP-level analog layout from schematics, including area estimation, floorplan optimization, routing, and layout verification. Perform LVS (Layout vs. Schematic) and DRC (Design Rule Check) debugging for advanced FinFET technology nodes (5nm, 7nm, 10nm, 14nm and below). Ensure layout quality by applying principles of matching, electromigration (EM), electrostatic discharge (ESD), latch-up prevention, shielding, parasitic management, and short channel effects. Utilize industry-standard EDA tools such as Cadence Virtuoso Editor and Calibre RVE for layout and verification tasks. Primary Skills : Analog Layout Design(Block/IP level) LVS/DRC Debugging FinFET Technology Node Experience(5nm, 7nm, 10nm, 14nm and below) EDA Tools Cadence Virtuoso Editor Calibre RVE Layout Optimization Area estimation Floorplanning Routing Secondary Skills : These support the primary responsibilities and enhance performance: Understanding of Physical Design Concepts: Matching Electromigration (EM) Electrostatic Discharge (ESD) Latch-Up Shielding Parasitics Short Channel Effects Critical Thinking & Problem Solving Interpersonal and Communication Skills Team Collaboration Educational Qualification: Bachelor's or Master's Degree.

: To work independently on block/IP levels analog layout design from schematic. Estimating the Area, Optimizing Floorplan, Routing and Verifications. Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 5,7,10, 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence Virtuoso Editor & Calibre RVE Good interpersonal skills and critical thinking abilities to resolve the issue technically, and professionally. Key Responsibilities: Independently execute block/IP-level analog layout from schematics, including area estimation, floorplan optimization, routing, and layout verification. Perform LVS (Layout vs. Schematic) and DRC (Design Rule Check) debugging for advanced FinFET technology nodes (5nm, 7nm, 10nm, 14nm and below). Ensure layout quality by applying principles of matching, electromigration (EM), electrostatic discharge (ESD), latch-up prevention, shielding, parasitic management, and short channel effects. Utilize industry-standard EDA tools such as Cadence Virtuoso Editor and Calibre RVE for layout and verification tasks. Primary Skills : Analog Layout Design(Block/IP level) LVS/DRC Debugging FinFET Technology Node Experience(5nm, 7nm, 10nm, 14nm and below) EDA Tools Cadence Virtuoso Editor Calibre RVE Layout Optimization Area estimation Floorplanning Routing Secondary Skills : These support the primary responsibilities and enhance performance: Understanding of Physical Design Concepts: Matching Electromigration (EM) Electrostatic Discharge (ESD) Latch-Up Shielding Parasitics Short Channel Effects Critical Thinking & Problem Solving Interpersonal and Communication Skills Team Collaboration Educational Qualification: Bachelor"s or Master"s Degree.