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1.0 - 5.0 years

12 - 22 Lacs

Bengaluru

Work from Office

Role & Responsibilities Architect fully fault-tolerant, scalable quantum processors by crafting blueprints and error-correction strategies for next-generation devices, including patentable IP. Design, simulate and benchmark surface, LDPC and bosonic codes on noise-biased hardware; iterate solutions with cryo-control and fabrication teams. Build numerical tool-chains in Python/QuTiP/Qiskit to model error propagation, mitigation and gate-fidelity limits , delivering data-driven design insights. Prototype dynamical-decoupling and error-mitigation schemes that extend coherence and enable bias-preserving logical gates. Publish peer-reviewed papers, file patents and author internal DoE reports that steer roadmap and funding decisions. Champion rigorous peer reviews, mentor junior researchers and foster cross-functional knowledge-sharing. Skills & Qualifications Must-Have PhD/MS in Physics, Mathematics, Computer Science or allied field with a quantum focus. 3 + years designing quantum error-correction codes (surface, LDPC) and fault-tolerant architectures. Proficiency in Python, MATLAB and quantum-software stacks for large-scale simulations and data analysis. Hands-on experience with dynamical decoupling/error-mitigation techniques on experimental platforms. Strong record of peer-reviewed publications and successful research projects. Excellent problem-solving, communication and collaborative skills. Preferred Familiarity with noise-biased bosonic codes and autonomous error-correction methods. Experience writing DoE and experimental-improvement reports to guide hardware trials. Background in cryogenic control electronics, RF instrumentation or superconducting-qubit fabrication. Proven patent filings or open-source contributions in quantum technology. Exposure to GPU-accelerated simulators or distributed-computing workflows for quantum modelling. Engagement with industry consortia or standards bodies advancing quantum-error-correction research

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