4.0 - 6.0 years

0 Lacs

hyderabad, telangana, india

On-site

Position: Physical Design Engineer Experience: 4+ yrs Location: Bangalore, Hyderabad Notice Period: Preferably 0 to 45 days Summary: Strong expertise in Physical Design and RTL-to-GDSII implementation flow, including synthesis, floor planning, place-and-route, timing closure, and sign-off. Proven ability to close full-chip and block-level designs from RTL to GDSII, addressing timing, noise, power, IR drop, physical verification, and equivalence checks. Hands-on experience with advanced technology nodes (7nm, 5nm, and below), managing challenges related to performance, power, and area (PPA). Proficient in Synopsys and Cadence tool suites, including Fusion Compiler, ICC2, Design Compiler, Prim...

Posted 1 day ago

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RTL Design Lead L&T Technology Services

8.0 - 15.0 years

0 Lacs

bengaluru, karnataka, india

On-site

RTL Design Engineer with 8+ to 15 of Hands on experiences. Experience/proficiency in RTL design(Verilog/VHDL) architecture implementation using (coding in) hardware description (RTL) , IP Design, SoC Design and Integration Should have hands on experience in all the Design aspects, should work independently. Experience/proficiency in front-end (logic) design of large complex high-speed digital stems from Specification to RTL code signoff Experience on RTL signoff tools, Lint, CDC, FE BE, Equivalence checks, Spyglass and other equivalent tools Strong team player & effective in communication

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