Senior Memory Design Lead Engineer ACL Digital

8.0 - 12.0 years

0 Lacs

karnataka

On-site

As a Senior Memory Design Lead Engineer, you will be responsible for developing memory compilers and memory Fast Cache instances for the next generation Cores in order to achieve outstanding PPA. Key Responsibilities: - Understanding of computer architecture and concepts. - Basic understanding of CMOS Transistors and their behaviors. - Understanding of high speed/low power CMOS circuit design, clocking scheme, Static and complex logic circuits. - Understanding of Power versus Performance versus Area trade-offs in typical CMOS design. - Having an engineering demeanor and Passion for Circuit design. - Good interpersonal skills are expected. - Minimum 8+ Yrs of experience in SRAM / memory design Margin, Char and its related quality checks. Qualifications Required: - Minimum 8 years of experience in SRAM / memory design Margin, Char and its related quality checks. - Understanding of computer architecture and concepts. - Basic understanding of CMOS Transistors and their behaviors. - Understanding of high speed/low power CMOS circuit design, clocking scheme, Static and complex logic circuits. - Understanding of Power versus Performance versus Area trade-offs in typical CMOS design. If you are interested in this position, you can apply or share your profile at Krishnaprasath.s@acldigital.com.,

Posted 19 hours ago

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