492 Eda Tools Jobs - Page 9

In this position you will be integrated in our Foundry IP Development team in Bangalore. In close collaboration with other disciplines across our worldwide engineering teams you will be developing layout for Std cell IP which enable our customers to perform product designs at highest quality standards based on Globalfoundries advanced process nodes. Job Responsibilities The development of product grade Standard Cell IP covering the following phases: Layout Design of Standard Cell IPs Layout checks like LVS, DRC, DFM, EMIR Review of Layouts and extend help for other Layout teams Design Kit prep from layout side, verification and validation Layout automation and script support Being a good tea...

The development of product grade Standard Cell IP covering the following phases: Layout Design of Standard Cell IPs Layout checks like LVS, DRC, DFM, EMIR Review of Layouts and extend help for other Layout teams Design Kit prep from layout side, verification and validation Layout automation and script support Being a good team player, taking key initiatives for productivity improvements and innovation Sign off and release into dedicated IP validation test chips Specification and documentation Support of silicon bring up and characterization Required Qualifications: Bachelor s degree with 10+ years or master s degree with 8+ years experience in semiconductors / Microelectronics / VLSI enginee...

Role: Design Verification Experience: 8+Years Location: Bangalore (WFO) Timings: IST 8+ years of design verification experience. MS (or higher) in EE/EC/ECC Engineering As a member of the Design Verification [Pre-Silicon DV] Team for NXP WCS/SCE BU You will be responsible for verification of various IPs and/or SoC. Candidate must be self-motivated and capable of working independently or as part of a team You will implement simulation testbenches, low power simulation setup, assembly/C language diagnostics, assertion checkers or coverage monitors to meet target verification goals. You will also assist with developing test-plans, debugging failures and analyzing coverage information. Must have...

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the worlds most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity t...

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the worlds most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity t...

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities Perform EMIR (Electromigration and IR drop...

As a Senior Physical Design Engineer with Micron Technology, you will play a crucial role in the HBM Team based in Hyderabad, India. Your primary responsibility will be to design and develop complex Application-Specific Integrated Circuits (ASICs) catering to the requirements and specifications of High Bandwidth Memories (HBM). These memories are utilized in intensive applications like artificial intelligence and high-performance computing solutions, aiming to push the boundaries of technology and innovation. Your role involves designing IPs or Hierarchical blocks solutions for high-performance and low-power applications. You will collaborate closely with cross-functional teams to define pro...

At AMD, we are dedicated to transforming lives with our cutting-edge technology to make a positive impact on our industry, communities, and the world. Our goal is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. Central to our mission is the AMD culture, where we continuously strive for innovation to address the world's most pressing challenges. We are committed to achieving excellence in execution while upholding values of directness, humility, collaboration, and inclusivity of diverse perspectives. As a SOC Physical Design Director at AMD, you will play a ...

Millions of people experience Synaptics every day. Your work impacts how people see, hear, touch, and engage with a wide range of IoT applications - at home, at work, in the car or on the go. You will be solving complex challenges alongside the most influential companies in the industry, utilizing advanced algorithms in areas such as machine learning, biometrics, and video processing, combined with world-class software and silicon development. Synaptics is currently seeking a Principal Design for Test Engineer to join our dynamic and growing organization. In this role, you will be responsible for architecting methodologies and flows for WLAN DFT, ATPG, automation, and pre/post Silicon debug....

As a Senior Member of Technical Staff (SMTS) Silicon Design Engineer at AMD, you play a crucial role in the physical design and implementation of advanced semiconductor chips. Your main responsibility is full-chip floor planning, collaborating closely with RTL designers, physical design teams, and other cross-functional groups. This role requires a solid understanding of physical design and chip architecture, as well as experience in floor planning tools and methodologies for high-performance and low-power design. Your technical expertise should include proven experience in top-level floor planning/block partition, SOC floorplan aspects, proficiency in EDA tools like Cadence, Synopsys ICC, C...

At Cadence, we are seeking a talented individual to join our team and contribute to the world of technology. In this role, you will collaborate closely with various cross-functional teams across different locations to ensure alignment on project goals and deliverables. Your responsibilities will also include mentoring junior engineers, fostering innovation, and driving automation initiatives. The ideal candidate should hold a BE/B.Tech/M.E/M.Tech degree with at least 7 years of relevant work experience. A strong understanding of Design for Testability (DFT) concepts and excellent communication skills are essential. Additionally, hands-on experience with industry-standard EDA tools and logic ...

Role & responsibilities Handling hierarchical scan insertion ATPG flow. Integration and Verification of MBIST at RTL level. RTL Integration, Verification, gate level Coverage and GLS enablement for LBIST. Implementation and Verification of IEEE1149.1 JTAG, IJTAG standards. Post silicon debug activities for DFT patterns. Collaboration with RTL design, Physical design and verification teams will be a daily aspect of the role. Preferred candidate profile Degree/PG in Electrical/Electronic Engineering, Computer Engineering or Computer Science. At least 12+ years of experience in related domains and have working knowledge of industry standard digital EDA toolkits. Must be conversant on EDA tools ...

Staff Analog Design Engineer Responsibilities: Developing low-power, high-performance analog circuits, including low phase noise/precision oscillators, DACs, and LDOs, in advanced process nodes. Defining circuit implementation architecture based on specifications, creating transistor-level designs, and collaborating with analog layout designers for optimization. Creating and maintaining documentation for designs, including specifications, test plans, usage guidelines, and limitations. Collaborating with system architects, the analog design team, and the DV (Design Verification) team for modeling and digital/mixed-signal top verification. Mentoring junior designers and sharing best practices ...

We are seeking an exceptional Senior Physical Design Engineer to take a key role in our semiconductor design team. As a Senior Physical Design Engineer, you will lead the development and implementation of cutting-edge physical design methodologies and flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensure the successful delivery of high-quality designs Key Responsibilities Perform Synthesis, floor planning, placement, Clock, routing, and PPA optimization for High Speed Advance ASICs. Define and drive physical design strategies to meet aggressive performance, power, and area targets. Conduct detailed analysis of timing, power, and area, and drive de...

Conduct classroom and online training sessions on VLSI design and verification. Teach HDL languages (Verilog, VHDL, SystemVerilog) and ASIC/FPGA design flows. Send Resume to : kalyangalactix@gmail.com Call : 7993047034 Provident fund

he ideal candidate should be passionate about software engineering and possess leadership skills to drive sophisticated issues to resolution. Able to communicate effectively and work optimally with different teams across AMD. A good understanding of FPGA is beneficial KEY RESPONSIBILITIES: Work with AMD's architecture specialists to improve future products Apply a data minded approach to target optimization efforts Stay informed of software and hardware trends and innovations, especially pertaining to algorithms and architecture Design and develop new groundbreaking AMD technologies Participating and leading new FPGA software and hardware bring ups Debugging/fix existing issues and research ...

At Cadence, we are in search of a candidate with a strong technical background, excellent communication skills, and the ability to quickly adapt to new technologies. This is an exciting opportunity to work in an environment that fosters creativity, innovation, and making a real impact. Our company's focus is on electronic design, utilizing over 30 years of software expertise to bring design concepts to life. We cater to a wide range of industries, including consumer electronics, 5G communications, automotive, and healthcare, among others. As part of the Cadence team, you will have the chance to work with cutting-edge technology and be encouraged to think outside the box. Our employee-centric...

We are seeking a highly skilled and experienced Principal Engineer to join our ASIC Development Engineering team in Bengaluru, India. In this role you will design and implements IPs and subsystems. Dealing the best of class IPs for all SanDisk products BE or Masters in Electronics or Electrical Engineering, Computer Engineering, or a related field 8+ years of experience in ASIC development, with a proven track record of leading complex project At hands on in IP / blocks / subsystem complex design in verilog / sysverilog Strong digital design development and execution skills , solving bugs Experience in grooming team of 1-4 engineers, interacting with many team Deep expirience in debug , solv...

Job Description Need to work in collaboration with global design teams across sites. Will be responsible for driving innovation in Analog IP designs. Responsible for design of IPs like Switched capacitor circuits , Voltage regulators, LDO, Current and Voltage reference, High Voltage charge pumps, temperature sensors, oscillators etc using industry standard EDA tools. Should provide technical leadership and mentor junior engineers. Responsible for developing processes and robust design methodology. Help build overall competency in Analog domain. Qualifications Bachelors/ Masters degree in Electrical/ Electronics Engineering with 8+ years of experience in Analog Circuit Design across different...

We are looking for a highly skilled Synthesis & Static Timing Analysis (STA) expert to join our Flows & Methodologies Team in Noida with a hybrid work model where you will be required to work 3 days in the office. As an ideal candidate for this role, you should have a minimum of 6 to 15 years of experience along with strong analytical skills, attention to detail, and the ability to collaborate effectively with cross-functional teams. Proficiency in EDA tools and digital design principles is a must-have for this position. Your key responsibilities will include working closely with SoC cross-functional teams to define and develop Synthesis & STA methodologies for advanced nodes such as 3nm, 5n...

We are looking for a highly skilled and experienced PDN (IR Drop & EM analysis) & PV (Physical Verification) expert to be a part of our Flows & Methodologies Team. This role necessitates strong analytical capabilities, meticulous attention to detail, and effective collaboration with cross-functional teams. Proficiency in EDA tools along with a comprehensive understanding of digital design principles are crucial for excelling in this position. The position is based in Noida and follows a hybrid model with 3 days in the office. The ideal candidate should have 6 to 15 years of relevant experience in the field. Key Responsibilities & Skills: - Collaborate closely with SoC cross-functional teams ...

You are an experienced Design-for-Test (DFT) Engineer with over 5 years of hands-on expertise in DFT methodologies and implementation. You should possess a solid understanding of MBIST, Scan, ATPG, and simulation concepts, along with a proven track record of executing industry-standard DFT flows. Your key responsibilities will include performing MBIST insertion, Scan insertion, and ATPG pattern generation using industry-standard EDA tools. You will be conducting MBIST simulations and analyzing results using tools from Cadence, Siemens Tessent, or Synopsys. Additionally, you will execute zero delay and SDF-based timing simulations, and efficiently debug issues using simulators such as VCS, NC...

Job Description Position: IO Layout Engineer Location: Bangalore, India Duration: Full Time Responsibilities: Custom layout development on block level to Top level I/O layout for GPIO, HSTL, HCSL, VTMON, LVCMOS, DDR, LVDS etc. Knowledge on Latchup, ESD and EM. Exposure to lower nodes N3E, 5nm etc. Skills: LVS/DRC/ERC/Litho Checks/Antenna/ESD-LU/Density etc. Should possess good knowledge on CMOS functionality, CMOS fabrication process, foundries and challenges in latest technology nodes. Well experienced in using industry standard EDA tools like Cadence Virtuoso, Mentor Graphics Caliber etc. Good problem solving and logical reasoning skills. Good communication skills required. Qualifications:...

Roles & Responsibilities : Hands on experience in developing Analog Layout / IO layout design. Good exposure on FinFet layouts in lower nodes. Expertise in using the best and latest features of Cadence and Calibre DRC/LVS. Good exposure on ESD, LUP, antenna layout challenges and analysing/fixing EMIR issues. Capable of working independently and with team and getting work done. The ability to work communicate effectively with global engineering teams.Able to handleAnalog Layout Design, EDA Tools, DRC, LVS, Calibre, FinFet Secondary Skills Knowledge in Cadence, Virtuoso, Physical verification.

As an Electrical Engineer at our company, you will be responsible for contributing to the development and maintenance of cutting-edge TPU (Tensor Processing Unit) technology that powers Google's AI/ML applications. Your expertise in emulation systems, EDA tools, and programming/scripting languages will be crucial in supporting our ASIC projects and ensuring their successful verification and bring-up. Your primary role will involve working on the emulation infrastructure, tools, and workflow methodologies that are essential for the prototyping of ASICs. By collaborating with cross-functional teams and external vendors, you will help drive the innovation behind our custom silicon solutions and...