492 Eda Tools Jobs - Page 8

About MIPS MIPS is a leader in high-performance RISC-V CPU IP, enabling innovation across automotive, AI, data center, and embedded markets Our engineering teams are building the next generation of compute solutions, and we are looking for passionate talent to join us in shaping the future of semiconductors, Position Overview The DFT Manager leads and develops the engineering team responsible for designing and deploying advanced Design-for-Test solutions in semiconductor chip development This role focuses on building robust DFT architectures?including ATPG, MBIST, LBIST, analog test solutions?and implements repeatable methodologies and flows that ensure rapid, optimized test pattern generati...

As an experienced Functional Formal Verification Engineer, you will be leading the formal verification efforts for complex digital designs. You will play a critical role in ensuring the quality and reliability of our digital designs. **Key Responsibilities:** - Lead complete formal verification for single or multiple design blocks and IPs, including developing and implementing formal verification strategies and test plans. - Create comprehensive formal verification test plans and specifications to ensure thorough coverage of design functionality. - Prove design properties, identify bugs, and collaborate with design teams to improve micro-architectures and ensure design correctness. - Craft i...

We are seeking an experienced System on Chip (SoC) Architect to join our development team. The ideal candidate will be involved in designing, integrating, and optimizing SoC hardware architectures and ensuring seamless software-hardware co-development. You have: Bachelors Degree in Electrical Engineering, Computer Engineering, or a related field (Masters or Ph.D. preferred). Overall,15+ years of experience as a Chip design expert. 8+ years of proven experience in IC design, SoC architecture, or a similar role. Proficiency in hardware description languages: Verilog, VHDL, and System Verilog Expertise in EDA tools for IC design and verification: Mentor Graphics, Cadence, or Synopsys Strong und...

As a Staff Software Engineer at Qualcomm India Private Limited, with a minimum of 10-15 years of experience in Electronic Design Automation (EDA), your role will involve designing, deploying, and scaling software platforms that integrate Machine Learning with semiconductor design, aimed at revolutionizing chip development workflows. **Key Responsibilities:** - Design and develop end-to-end ML-integrated EDA software platforms for scalability, performance, and adaptability. - Establish software development processes incorporating best practices and agility. - Create advanced algorithms for automation and optimization in EDA flows. - Engineer reliable and scalable data pipelines to support ML ...

Role Overview: As a Physical Design Engineer specializing in memory layout within leading TSMC process technologies (7nm and below), you will be responsible for designing and developing memory layouts such as SRAM, ROM, and Register Files. Your focus will be on optimizing performance, area, and power efficiency to ensure design integrity and compliance with foundry requirements. This role will allow you to collaborate with global teams and work on cutting-edge technology nodes. Key Responsibilities: - Design and develop memory layouts in advanced process nodes (TSMC 7nm, 5nm, 3nm, 2nm). - Implement layout including floorplanning, placement, routing, and parasitic extraction. - Collaborate wi...

As a Staff Software Developer specializing in Machine Learning for EDA Systems at Qualcomm India Private Limited, you will play a crucial role in designing and implementing cutting-edge machine learning techniques in the realm of Electronic Design Automation (EDA). Your primary responsibilities will revolve around leading software development initiatives, guiding a team of engineers and ML practitioners, and ensuring the seamless integration of ML into semiconductor design workflows. Below are the key details of the job: **Role Overview:** You will be responsible for designing and developing end-to-end ML-integrated EDA software platforms, leading a team of engineers, refining software devel...

About The Role : To work independently on block/IP levels analog layout design from schematic. Estimating the Area, Optimizing Floorplan, Routing and Verifications. Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 5,7,10, 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence Virtuoso Editor & Calibre RVE Good interpersonal skills and critical thinking abilities to resolve the issue technically, and professionally. Key Responsibilities: Independently execute block/IP-level analog layout from schematics, including area estimation, floorplan optimizat...

Who You'll Work With You will be in the Silicon One development organization as an ASIC DFT Engineer in Bangalore India with a primary focus on Design-for-Test. You will work with DFT Lead, Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a member of this team you will also be involved in crafting groundbreaking next generation networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases with additional exposure to physical design signoff activities. What You'll Do Responsible for implementing the Hardware Design-for...

Job Requirements PD Trainee Engineer Role Summary: We are looking for enthusiastic entry-level engineers to join our VLSI Physical Design (PD) team. As a trainee, you will learn and contribute to various stages of the chip design flow under the guidance of Lead engineers. Key Responsibilities: Assist in physical design activities such as floor planning, placement, clock tree synthesis, routing, and timing closure. Work with senior engineers to run EDA tools for design implementation and verification. Support design checks for power, performance, and area (PPA). Learn industry-standard flows for DRC, LVS, and STA. Document processes and contribute to knowledge sharing within the team. Work Ex...

Responsibilities Understand the standards/specifications Architecture development and documenting implementation level details Hands on work for every aspect of verification cycle Responsible for the compliance with the latest Methodologies. Developing Verification IPs Define Functional Coverage matrix and Comprehensive Test plan Regression management and functional coverage closure DUT integration and verification for IP delivery sign-off Leading small team Person Specification Required Skills Hands-on experience of complete verification cycle with strong verification concepts Strong knowledge of Verilog, SystemVerilog and UVM Experience in UVM based Verification IP development Experience i...

As a Hardware Design Engineer at Netweb Technologies, you will play a crucial role in project deliverables by creating detailed design specifications, schematics, and Bill of Materials (BOM). Your responsibilities will include collaborating with cross-functional teams, comprehending design requirements, formulating system/subsystem designs, and actively engaging in design reviews. You will focus on designing schematics for digital, mixed-signal, and power electronics circuits that align with the project's requirements. Additionally, you will interact with PCB layout teams to finalize component placement considering Mechanical and Signal Integrity/Power Integrity (SI/PI) constraints. Your rol...

Job Details Job Description: Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff include formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to fix violations for cu...

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer ...

Job Summary We are seeking an experienced GLS Lead to drive gate level simulation activities, including power-aware GLS, formal verification, and MCP verification. The ideal candidate will lead a team of engineers, ensuring timely delivery of all verification projects and maintaining high quality standards. Key Responsibilities Lead and manage the GLS team, providing technical direction and mentorship. Plan, execute, and oversee gate level simulation (GLS) flows for complex SoC designs. Drive power-aware GLS and ensure coverage of low power verification scenarios. Oversee formal verification and MCP verification activities, ensuring completeness and correctness. Collaborate with design, DV, ...

We are looking for passionate and skilled Standard Cell Characterization Engineers to join our semiconductor design team in Bangalore. The role involves development, characterization, and validation of standard cell libraries to ensure optimal performance, power, and area (PPA). Responsibilities: Develop and support standard cell libraries. Perform PPA trade-off analysis between different cell architectures. Collaborate with layout team on floor plan, schematic, and layout guidelines. Design and implement combinatorial, sequential, and power management circuits. Run equivalence verification (e.g., ESPCV). Characterize and generate library views across multiple PVT corners. Support PnR, Simul...

Expertise : Power fundamentals Good knowledge of PTPX Good knowledge of CLP Knowledge of design verification, RTL coding, synthesis, and physical design Protocol knowledge of , DDR, CHI, Cache, computer organization, bus protocol, Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year ...

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Enginee...

General Summary: As a Qualcomm Machine Learning Engineer, you will create and implement machine learning techniques, frameworks, and tools that enable the efficient discovery and utilization of state-of-the-art machine learning solutions over a broad set of technology verticals or designs. Qualcomm Engineers collaborate with cross-functional teams to enhance the world of mobile, edge, auto, and IOT products through machine learning hardware and software. Minimum Qualifications: Bachelor's degree in Computer Science, Engineering, Information Systems, or related field and 4+ years of Hardware Engineering, Software Engineering, Systems Engineering, or related work experience. ORMaster's degree ...

The Physical Design Manager role at MIPS involves leading and guiding teams in the creation of custom integrated circuits (ICs) to meet specific customer requirements. You will oversee the entire physical design process, from synthesis to verification, ensuring project efficiency, quality, and innovation. Your responsibilities will include managing a team of physical design engineers, developing design strategies, maintaining re-use methodologies, and collaborating with cross-functional teams and customers to deliver optimized solutions. You should have a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field, along with at least 5 years of experien...

You will collaborate with system architects and micro-architects to define high-level, implementable SoC specifications. Your responsibility will include owning end-to-end SOC RTL delivery while analyzing and optimizing design for power, performance, and area (PPA) targets. You will influence SoC definition, features, and adopt physical design friendly partitioning. Leading RTL design and integration of multi-subsystem SoCs, supporting complex architectures with multi-core, multi-power, and multi-reset domains will be a key aspect of your role. Demonstrating strong proficiency with front-end flows, including Lint, CDC, low-power (UPF) checks, synthesis, DFT, and Static Timing Analysis (STA) ...

As a Design Engineer-2 FPGA Architecture at Lattice Semiconductor, you will be part of a dynamic team focused on FPGA architecture modeling and system architecture advancements. You will have the opportunity to contribute, learn, innovate, and grow within a fast-paced, results-oriented environment. Your responsibilities will include working in RTL design, utilizing best-in-class coding styles, algorithms, and both Verilog and System Verilog. You will be involved in architecture modeling and evaluation of Lattice FPGAs and Software tools to measure performance, power, and area for various workloads. Additionally, you will drive subsystem development, ensuring designs meet high standards of qu...

As an Analog Design Engineer in the Consumer Audio Amplifier Group, you will be responsible for designing and developing state-of-the-art audio amplifiers. You will work with a team of experts in the industry, focusing on Audio CLASSD Amplifier with High-Voltage designs and precise current sensing. Your role will involve managing and leading product development, developing circuits, and influencing decisions that impact various products and teams. You will have the opportunity to work on cutting-edge analog and power semiconductor processes, interact with wafer fabrication facilities, and learn about product development processes, qualification, and manufacturing flows. Additionally, your ro...

As an FPGA Architect at NEC Corporation India Pvt. Ltd, you will be responsible for designing and implementing high-performance FPGA designs for wireless communication and aerospace systems. You will conduct research and development activities related to logical synthesis, netlist partitioning, placement, and routing optimizations for FPGA prototyping. Your role will involve optimizing FPGA designs for latency, throughput, power, performance, and area efficiency. Additionally, you will evaluate and select appropriate technologies and tools to support the development process, collaborating with cross-functional teams to align on product requirements and technical specifications. You should po...

You should have a strong understanding of EDA tools and flows, with specific experience in Tempus/Primetime. Your expertise should include timing closure (STA) and various timing closure methodologies. You will be responsible for pre/post-layout constraint development towards timing closure and collaborating with the design team to establish functional/DFT constraints. Additionally, you will need to integrate IP level constraints and define multi-voltage/switching aware corners. An understanding of RC/C model selection and expertise in abstraction techniques such as Hyperscale/ILM/ETM will be crucial for this role. You will also be expected to perform RC balancing and scaling analysis for fu...

Alternate Job Titles: ASIC Physical Design Manager We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and accomplished leader with a deep-rooted expertise in ASIC physical design, ready to take on the challenge of managing complex chip projects from conception to tapeout. With 10-15 years of experience in the ...