165 Eda Tools Jobs - Page 5

Need to work in collaboration with global design teams across sites. Will be responsible for driving innovation in Analog IP designs. Responsible for design of IPs like Switched capacitor circuits , Voltage regulators, LDO, Current and Voltage reference, High Voltage charge pumps, temperature sensors, oscillators etc using industry standard EDA tools. Should provide technical leadership and mentor junior engineers. Responsible for developing processes and robust design methodology. Help build overall competency in Analog domain. Qualifications Bachelors/ Masters degree in Electrical/ Electronics Engineering with 8+ years of experience in Analog Circuit Design across different technologies. Should have experience in developing analog IPs like Switch capacitor circuits, LDO, DC-DC convertor, oscillator, ADCs, Should have experience in integrating Analog IPs in a complex system. Knowledge of PCB and system design will be preferred. Should experience in silicon characterization and probing. Should have experience in a multi-site environment, interacting with teams in other sites. Should possess good mentorship skills. Ability to coordinate priorities and initiatives

Strong program management skill design and development of Automotive Interior Body Trims IP console. Experience in A, B, C pillar trims, Dashboard assembly, Front and Rear Door Trims, Center Console, Side panels Trims, head liner, Sunroof. Having god experience in Floor carpet, Headliners, NVH.

Strong program management skill Upper Body, Underbody, Closure, Surfacing, Sheet metal manufacturing, stamping feasibility. A class surface, mastersurface preparation, style feasibility, Body structure, Outer panel, inner panel, reinforcements, doors.

Strong program management skill with a goal/target minded discipline process excellent communication and interpersonal skills. Experience in Exterior Body trims such as front body bumper, Grill, Side cladding, Wheel arch, Rear bumper, Mudflap

Job Description Position: - Sales Engineer Qualification: BE/ B Tech. in Electronics Experience: 2- 5 Years Location: Delhi/Hyderabad/Pune/Kolkata No. of positions: 10 The Sales Engineer is a customer facing role, responsible for the complete sales process - demand creation, mapping of accounts and closure. The candidate should be able to effectively communicate EDA / MCAD product capabilities and the benefits of the solutions through presentations and sales demonstrations. Conduct discovery and requirements gathering sessions to analyze and understand customer needs, workflows and technical requirements. Develop and/or collate sample documents, applications and other sales enablement materials for use during the sales and marketing sessions. Collaborate with Technical and services teams to specify, recommend and architect comprehensive customer solutions Required Skills : Relevant Sales experience in Defense / Institutional Sales /Private Commercial Sales/Academics Sales experience in Application or Engineering Software Knowledge on EDA tools Siemens EDA / Cadence / Synopsys Knowledge on MCAD tools Cero (ProE)/UGNX/Catia/Solid edge/Solid works/Inventor Knowledge on CAE Tools Ansys/Nastran/Adams/Altair Knowledge of Procurement procedures such as Tender, Gem portal, E-tender, etc. Must be aware about the complete sales cycle Responsibilities: Identify customer needs and recommend suitable products/solutions Deliver product/concept presentations and conduct industry seminars Resolve client queries and manage sales concerns Capable of analyzing the merit of opportunities Skilled in identifying customer pain points Soft Skills: Team-oriented with strong analytical and presentation skills Creative, confident, and proactive Able to perform under pressure and meet targets Culturally adaptable with strong convincing skills Willing to travel extensively (7075%)

We are looking for a Senior HPC Engineer to join our IT Infrastructure Engineering & Application (IE&A) group. You will play a critical role in managing high-performance compute environments, automating solutions, and supporting engineering teams across Arm. If you are passionate about HPC systems and want to work on global infrastructure projects, this is the role for you! Roles & Responsibilities: Administer and support IBM Spectrum LSF clusters Develop and maintain automation scripts using Bash, Shell, Python, or Perl Work with public cloud platforms such as AWS, GCP, or Azure Handle ticket-based support and proactively resolve infrastructure issues Collaborate on key engineering projects to enhance system resilience and security Mandatory Key Skills: 1. IBM Spectrum LSF Administration 2. Linux (RedHat) System Administration 3. Bash/Shell/Python/Perl Scripting 4. Public Cloud Platform (AWS/GCP/Azure) 5. Automation & DevOps Tools (Terraform/Ansible/CI/CD)

Technical Leadership Schematic Design Development boards Hardware Development RF Design & Wireless Tech: Hands-on exp. with RF layout practices, impedance matching, antenna selection/integration, (LoRa, BLE, Wi-Fi, GSM, NB-IoT, GPS). EDA Tools Required Candidate profile Bachelor or Master's Electrical Eng, Electronics Eng. related field. Min 6-7 years exp electronics hardware design, development, with focus on schematic design. Basic knowledge of Embedded-C, Python

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. J Principal Responsibilities: Senior leader with 20+ CAD/Methodology development experience for team in Bengaluru. Drive tools, flows, methodologies globally as part of world-wide CAD organization. Develop and implement advanced CAD flows and methodologies for front end RTL Design to Verification Methodologies and framework development. Utilize scripting languages (python) to automate CAD/IT processes and increase efficiency. Collaborate with cross-functional teams to ensure successful integration of CAD flows. Stay up-to-date with cutting-edge technology (AI/ML), conduct thorough analysis of CAD tools and make improvements. Work closely with users to troubleshoot and resolve any issues that arise in tools, flows, environment, and infrastructure. Preferred Qualifications: Experience building full stack AI applications, with a focus on practical, production-grade solutions Strong proficiency in Rust for performance-critical systems and Python for AI development and scripting . Solid understanding of large language models (LLMs), their mechanics, and their real-world applications. Experience implementing tool use capabilities for LLMs and agent frameworks Knowledge of evaluation methodologies for fine-tuned language models Good grasp of Retrieval-Augmented Generation (RAG) and latest AI Agent frameworks Ability to stay current with the fast-evolving AI landscape]. Including advancements in LLMs and neural networks Strong understanding of CAD/EDA tools and methodologies. Hands on experience with regression systems, CI/CD, Revision Control System (git, perforce) workflow. Strong fundamentals in digital design, design verification methodologies and EDA tools. Knowledge of SOC architecture is a plus Preferred – Masters in VLSI or Computer Science Minimum – Bachelors in Electronics/Electrical Engineering/Computer Science Atleast 15 years’ experience in development of tools/flows/methodologies in either RTL, DV, synthesis, PnR or Signoff. Should have a proven record of driving new innovative tool/flow/methodology solutions. Should have managed a medium sized team. Level of Responsibility: Works independently with minimal supervision. Work with chip leads in support of design verification. Collaborate with chip leads to understand the design methodology. high-level requirements, determine other areas to support current or future designs that can benefit from automation and tooling. Provides supervision/guidance to other team members. Decision-making is significant in nature and affects work beyond immediate work group. Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc.

Greetings from Tamilnadu Advanced Technical Training Institute (TATTI)! We are looking for an experienced Verilog and VHDL Trainer to deliver practical and conceptual training in digital system design. The role involves guiding learners through hands-on sessions using industry-relevant tools, preparing them for roles in the semiconductor and embedded systems domain. Job Type: Freelance Location: Chennai Key Responsibilities: Conduct training sessions on Verilog and VHDL Develop course materials, lab exercises, and projects Mentor learners and support project development Stay updated with trends in FPGA, ASIC design, and EDA tools Requirements: Proficiency in Verilog and VHDL Experience with tools like ModelSim, Vivado, Quartus etc. Strong communication and presentation skills Prior teaching/training experience is a plus Why Join TATTI Work with a renowned technical training institute with over 40 years of experience . Collaborate with leading corporate clients . Enjoy career growth and continuous learning opportunities. Be part of an innovative and dynamic team . Apply Now: Interested, Click the link to apply!

Job Description. Our Solutions Engineering Physical IP team comprises some of the industry’s leading experts in deep submicron circuit design. This position is a wonderful opportunity for you to work with our custom standard cell design engineering team on innovative technologies. Your work will have a significant lasting impact as the designs will be used in Solutions Engineering products servicing the infrastructure, client, automotive, and IoT market segments.. In this role, you will take significant responsibility for the technical leadership and strategic direction within the team. You will proactively identify and drive improvements in design processes, methodologies, and infrastructure to ensure continued excellence and innovation.. Responsibilities. Lead technical strategy and decision-making for key product or functional areas in standard cell development. Drive improvements to methodologies, tools, and processes, proactively inspiring change across project teams and related functions. Act as a recognized technical guide and mentor within your area, providing guidance and direction to other specialists across the team. Collaborate closely with multiple teams, projects, and partners across Arm, significantly influencing broader organizational outcomes. Develop Arm custom standard cells in the latest, sub-3nm process technology nodes. Co-optimize circuit designs with physical design engineers to improve PPA of Arm cores integrated into best-in-class SoCs. Closely collaborate with the mask design team for optimal layout tuning, library view characterization, modeling, and QA validation using diverse EDA tools. Required Skills And Experience. 10+ years of relevant circuit design experience (for BSEE), 8+ years (for MSEE).. Proven track record of providing technical leadership and strategic oversight on complex projects or across multiple teams.. Significant experience in identifying, designing, and verifying cells specifically targeted to improve core and SoC-level PPA.. In-depth understanding of MOSFET electrical characteristics, transistor-level device physics, PPA tradeoffs, layout, and variability especially at 3nm and below.. Expertise in transistor-level design of static circuits, including state-retaining elements like latches and flops.. Extensive hands-on development experience with standard cell EDA view characterization, modeling, and QA.. Proficiency with standard cell characterization tools and Spice circuit simulators.. Strong proficiency in scripting languages such as Perl or Python.. Demonstrated ability to independently resolve complex design and project issues, influencing decisions across multiple projects or departments.. Ability and willingness to proactively mentor and support the development of team members.. Demonstrated positive attitude, respect for team members, continuous skill development, and ability to handle diverse responsibilities effectively.. Strong analytical skills with the ability to clearly present conclusions and recommendations.. “Nice To Have”. Experience leading multi-functional technical initiatives, influencing senior customers, and handling project timelines and risks.. Exposure to physical design implementation flow and signoff.. Accommodations at Arm. At Arm, we want to build extraordinary teams. If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm.com . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process.. Hybrid Working at Arm. Arm’s approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing. We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility. Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the team’s needs. Details of what this means for each role will be shared upon application. In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution. Please talk to us to find out more about what this could look like for you.. Equal Opportunities at Arm. Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We are a diverse organization of dedicated and innovative individuals, and don’t discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.. Show more Show less

About the Role: We are seeking a talented and experienced Analog Layout Engineer to join our team in Bangalore. The ideal candidate will have a strong background in analog layout design and will contribute to the development of cutting-edge semiconductor products. If you are passionate about VLSI design and eager to work in a collaborative, innovation-driven environment, this opportunity is for you! Location: Bangalore Experience: 3 to 10 Years Employment Type: Full-Time Notice Period: 90 Days Key Responsibilities: 1. Design and implementation of custom analog and mixed-signal layouts for circuits such as amplifiers, ADC/DACs, PLLs, and more. 2. Perform layout verification tasks, including DRC, LVS, and parasitic extraction using industry-standard tools. 3. Optimize layout designs for performance, area, and power while ensuring compliance with design rules and process constraints. 4. Collaborate closely with circuit design engineers to interpret specifications and requirements. 5. Participate in design reviews and contribute to the enhancement of layout methodologies. 6. Work on advanced nodes, ensuring high-quality layouts for high-performance, low-power designs. Required Skills and Qualifications: 1. Experience: 3 to 10 years in analog layout design, with expertise in full-custom IC design. 2. Proficiency in layout tools such as Cadence Virtuoso, Synopsys Custom Compiler, or equivalent. 3. Strong knowledge of semiconductor process technologies, including FinFETs and advanced nodes (e.g., 7nm, 5nm). 4. Hands-on experience with parasitic-aware design, matching, and signal integrity. 5. Familiarity with EDA tools for verification, such as Calibre or Assura. 6. Excellent analytical and problem-solving skills with attention to detail. 7. Strong communication and interpersonal skills to work effectively in a team environment. What We Offer: 1. Competitive compensation package and benefits. 2. Opportunity to work on innovative and challenging projects. 3. Dynamic and collaborative work environment. 4. Career growth and learning opportunities.

• Sales experience in Application or Engineering Software • Knowledge on EDA tools – Siemens EDA / Cadence / Synopsys • Knowledge on MCAD tools – Cero (ProE)/UGNX/Catia/Solid edge/Solid works • Knowledge on CAE Tools – Ansys/Nastran/Adams/Altair

Physical Design Implementation: Experience in block and SoC level PD implementation, covering the entire flow from netlist to GDSII, including PnR/APR. Low Power Design: Proficient in low power design techniques. Flow Expertise: Hands-on experience with floorplanning, power planning, placement, CTS (Clock Tree Synthesis), routing, extraction, and DFM (Design for Analysis Skills: Strong ability to perform congestion and timing analysis, with a focus on achieving better QoR (Quality of Results). Sign-Off Expertise: In-depth knowledge of sign-off processes including STA (Static Timing Analysis), DRC/LVS/Antenna/ERC checks, power analysis, IR/EM analysis, LEC (Logic Equivalence Checking), and ECO (Engineering Change Order) for both Process Knowledge: Comprehensive understanding of the entire physical design process from RTL to GDSII, encompassing floorplanning, placement, CTS, routing, and sign-off stages. ECO Implementation: Experience in implementing ECOs. PnR Tools: Hands-on experience with PnR tools such as Synopsys ICC II and Scripting Skills: Proficient in scripting languages like Perl and TCL, with experience using various EDA tools. Expectations from the Role: Debugging & Problem-Solving: Excellent debugging and problem-solving skills, with the ability to tackle complex design issues. Communication: Effective communication skills for interacting with all Focus & Commitment: Must be highly focused and committed to achieving project goals and closing out tasks. Independence: Ability to work independently and manage tasks with minimal Leadership: Possesses strong leadership skills with a proactive, go-getter attitude.

Job Description : Full-chip DFT working experience with multiple design Tape Outs. Block level and Chip level SCAN insertion, DRC, Coverage Analysis and improvements. Expertise in Scan Compression(EDT/OPMISR+), MBIST, BSCAN, ATPG implementation and verification. Hands-on Experience with industry-standard DFT EDA tools and flows. Good Knowledge of cross-functional domains (SYN, LEC, STA, PD) with ownership of constraints developments and LEC. Excellent problem-solving and debugging skills. Proactive in nature. Develop/automate flows and scripts in Perl/Tcl to enhance the DFT methodologies and processes. Leading junior teams, Mentoring/Training and Project leadership. Excellent Customer interaction, Communication and Teamwork skills. Desired Skills : ATPG (at-speed and stuck-at), At Speed Scan, Design for Testability (DFT).

Position: DFT Engineer (ASIC) Experience: 2+ Years Location: Hyderabad Job Summary: We are seeking a talented DFT (Design for Testability) Engineer with expertise in ASIC design and a strong background in EDA tools such as Synopsys . The ideal candidate will have hands-on experience in developing, implementing, and optimizing DFT architectures to ensure high test coverage and manufacturability. Key Responsibilities: Design and implement DFT methodologies for ASIC projects, including scan insertion, ATPG, and BIST. Work with EDA tools from Synopsys (such as TetraMAX, DFT Compiler, TestMAX, etc.) to achieve high test coverage and efficient test solutions. Develop and validate test strategies for scan-based testing, MBIST, and boundary scan. Collaborate with RTL and physical design teams to ensure seamless DFT integration. Perform fault simulations , analyze test results, and drive improvements in test efficiency. Optimize DFT architectures for low-power, high-performance, and manufacturability . Support silicon bring-up and debug of test patterns on actual hardware. Work closely with foundries and test teams to ensure smooth production testing. Keep up to date with the latest DFT methodologies, trends, and innovations. Required Skills & Qualifications: 4+ years of experience in DFT implementation for ASIC designs. Proficiency in Synopsys EDA tools for test implementation and validation. Solid understanding of digital design, scan insertion, ATPG, and BIST . Experience with fault modeling, test coverage analysis, and debugging . Strong scripting skills in Python, Perl, or TCL for automation. Ability to work in a multi-disciplinary team and communicate technical concepts effectively. Preferred Qualifications: Experience with Post-Silicon Debug and ATE Testing . Knowledge of Verilog/VHDL and simulation tools . Familiarity with industry-standard DFT flows and methodologies .

This position is part of Seagate Research Group (SRG). Seagate delivers advanced digital storage solutions to meet the needs of today s consumers and tomorrow s applications. Through technology, leadership and innovation, Seagate continues to help individuals and businesses maximize the potential of their digital content in an ever-evolving, on-demand world. About the role - you will: Work full time on projects at Pune in assisting Seagate Research Architect/leads in the area of most cuttingedge research in storage technologies Be responsible for investigating emerging technologies in storing data efficiently, which create data in new frontiers from AI/ML/mobility Potentially explore new mechanisms in electronic hardware modeling and prototyping in processing the data using upcoming technologies such as computational storage securely Conduct surveys and process public and enterprise forums to help build models around these technologies, generate new ideas and conceptualize them with the help of senior engineers in the team, Contribute in the development of architecture towards building proofs of concepts Research/investigate emerging technologies in storage components and system, Data creation models and storage security Document current and future storage architectures for different applications Provide research intelligence for future Seagate products or create reference architectures Work with subject matter experts at all Seagate (worldwide) sites Create internal and external research papers and work with your affiliated school to bring academic research in these areas for applications in storage industry About you: Creative, independent and self-starter individual with excellent written and interpersonal communication Must be authorized to work in India while pursing education Must have working knowledge of Unix-based and Windows Operating Systems Teamwork is a core competency at Seagate, individual must be able to work and communicate effectively with a diverse group of engineers Must have demonstrated ability to study a functional area in depth Ability to present to colleagues and partners Graduate School Research level experience in C/C++ Programming Your experience includes: Exposure to hardware design focusing on board design and knowledge about EDA tools from Cadence or Mentor/Siemens is desirable Exposure to storage domain and embedded environments as we'll as programming in Python for AI/ML techniques is an added plus Hands on experience in C/C++ programming which is a basic requirement

Memory Architecture: In-depth knowledge of memory design architectures, including SRAM, DRAM, Flash, and other non-volatile memory types. Circuit Design: Expertise in designing memory cells, sense amplifiers, decoders, and other associated memory circuit blocks. Process Technology: Familiarity with advanced CMOS technology nodes and their impact on memory design, including scaling challenges. Design Optimization: Experience in optimizing memory for performance, power, and area, including techniques for reducing leakage and improving access times. Verification & Validation: Proficient in memory verification techniques, including corner analysis, reliability testing, and post-silicon validation. EDA Tools: Hands-on experience with memory design tools, including Cadence, Synopsys, and Mentor Graphics. Yield Enhancement: Knowledge of yield enhancement techniques, including redundancy and error correction codes (ECC). Expectations from the Role: Technical Leadership: Strong technical leadership skills with the ability to guide and mentor junior team members. Problem-Solving: Excellent problem-solving abilities, particularly in diagnosing and resolving memory design challenges. Innovation: Ability to innovate and drive improvements in memory design, balancing performance and manufacturability. Collaboration: Strong communication and teamwork skills, with the ability to work effectively with cross-functional teams. Project Focus: Ability to manage and prioritize multiple projects, ensuring timely

GlobalFoundries is seeking a highly motivated OPC/ORC Engineer to become part of the OPC team. This technical individual contributor will beresponsible for supporting GlobalFoundries advanced technology Optical Proximity Correction (OPC) and Optical Rule Check (ORC). Working on the leading edge technologies will provide an opportunity to develop new methodologies and business practices aimed at a highly efficient and world-class Data Prep operations. This position will be based in BLR, INDIA. Your Job: Develop and maintain OPC code (recipe) for various technodes Develop and maintain ORC code (recipe) for various technodes Work on different aspects of OPC code - like SRAFs, MRC, Booleans Do ORC review with required details and complete within agreed time Develop and maintain OPC code (recipe) for various technodes (like 12/14nm) supporting world wide fabs Develop and maintain ORC code (recipe) for various technodes (like 12/14>) supporting world wide fabs Work on different aspects of OPC code - like SRAFs, MRC, Booleans Do ORC review with required details and complete within agreed time Ability to work in a dynamic collaborative environment which requires strong teaming skills with Engineers, Technicians, Managers, and IT Interact with ??other GF Teams such as Fab Litho,Frame and Fab Integration Engineers to provide feedback to Release for D2M Reviews Disposition Ability to solve complex technical problems and contribute to multiple projects at the same time Strong ability to learn and explore new technologies, opportunities, and continuous improvement ?Familiarity with Fab processing is preferred Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs Required Qualifications: MS/MTech +internship is preferred Specialization on Microelectronics/VLSI or related fields Fluency in English Language - written & verbal Basic coding familiarity Exposure to Mentor graphics EDA tools and/or SVRF language Familiarity with perl or tcl or python or shell is a plus. Familiarity with OPC is a big plus

: 6 to 8 years of Semiconductor industry experience in Custom Mixed-Signal layout design with a bachelors degree in electrical/Electronic Engineering. Able to deliver Custom analog layouts independently from schematic to layout generation, estimating the area, optimizing floorplan, routing, and complete verification flows. Firsthand experience in critical analog layout design blocks such as Temperature sensor, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc. Good at LVS/DRC debugging skills and other verifications for lower technology nodes - 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence VLE/VXL, PVS, Assura and Calibre DRC/ LVS is necessary. Understanding layout effects on the circuit such as speed, capacitance, power, and area etc. Ability to understand design constraints and implement high-quality layouts. Multiple Tape out support experience and collaborating with cross functional teams will be an added advantage. Good people skills and critical thinking abilities to resolve the issue technically and professionally. Excellent communication. Responsible for timely execution with high quality of layout design. Multiple foundries experience is an added plus. Minimum Educational Qualification : Educational Bachelor's, Electrical or Electronics Engineering or equivalent Role And Responsibilities Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support. Perform layout verification like LVS/DRC/Antenna, EM, quality check and documentation. Responsible for on-time delivery of block-level/top-level layouts with acceptable quality. Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment. Guide junior team-members in their execution of Sub block-level layouts & review their work Should have good experience in working with cross-functional team. Ensure standard processes and procedures are followed to resolve all client queries. Handle technical escalations through effective diagnosis and troubleshooting of client queries Manage and resolve technical roadblocks/ escalations to timely deliverable with high quality. Troubleshoot all client queries in a user-friendly, courteous, and professional manner. Offer alternative solutions to clients (where appropriate) with the objective of retaining customers' and clients' business. Build people capability to ensure operational excellence and maintain superior customer service levels of the existing account/client. Contribute to effective project-management. Effectively communicating with engineering teams in different Geographical locations to assure the success of the layout project. Works in the area of Software Engineering, which encompasses the development, maintenance and optimization of software solutions/applications.1. Applies scientific methods to analyse and solve software engineering problems.2. He/she is responsible for the development and application of software engineering practice and knowledge, in research, design, development and maintenance.3. His/her work requires the exercise of original thought and judgement and the ability to supervise the technical and administrative work of other software engineers.4. The software engineer builds skills and expertise of his/her software engineering discipline to reach standard software engineer skills expectations for the applicable role, as defined in Professional Communities.5. The software engineer collaborates and acts as team player with other software engineers and stakeholders.

Position requires: Bachelor s degree with at least 1-3 years of design/EDA experience or Master s degree. Strong knowledge of Digital Design Fundamentals, Semiconductor Fundamentals and Static Timing Analysis Prior experience with ASIC digital implementation flows and EDA tools is required; Experience with advanced nodes (7nm and below) preferred. Good programming knowledge in Unix, Shell scripting, perl and importantly TCL Strong customer-facing communication and problem-solving skills Strong personal drive for continuous learning and expanding professional skill sets Excellent verbal and written communication skills Familiar with EDA tool operation, setup and debug: Digital: Genus, Innovus, Tempus, Voltus, etc Qualifications BE/BTech/ME/MS/MTech in Electrical/Electronic or equivalent

Job Description: Central product engineering role to liaison between R&D, Field engineering teams, along with product engineers within and other product teams. Test new product features through alpha and beta phases, identify and document usage scenarios, conduct Beta testing with interested customer counterparts and ensure successful deployment of new differentiating features. Study and improve usability, applicability and adoption of products, platforms and solutions to meet customer business needs. Diagnose, troubleshoot and resolve complex technical issues on customer installations Deploy and train customers on new implementations and capabilities. Review and analyze feedback on product and solutions performance from customers and other application partners Work directly with Research and Development (R&D) to develop and implement technical roadmap, specifications and validation for improvements and enhancements. Partner with customer technical leaders and Sales to identify business challenges, develop effective technical solutions for new accounts and increase utilization and retention of products on current accounts. Demonstrate creativity in building effecting test scenarios to exercise product features and identify issues as early as possible in development and deployment life cycles. Handle customer escalated situations with calm demeanor and create alternative solutions to un-gate critical engagements and production stop scenarios. Requirements: Typically requires a minimum of 5 years of related experience. Possesses solid background in Spice simulations (HSPICE, FineSim and industry standard simulators) with ability to create and work with spice decks and netlists. Experienced in standard cell characterization and basic concepts of timing (NLDM, CCST, CCSN), power (NLPM, CCSP), noise (CCSN), LVF, AOCV/POCV methodologies. Resolves issues in creative ways. to create usable workarounds and alternative solutions. Exercises independent judgment in selecting methods and techniques to obtain solutions. Executes projects from start to completion. Contributes to moderately complex aspects of a project Determines and develops recommendations to solutions. Works on team-driven or task-oriented projects. Networks with senior internal and external personnel in own area of expertise. Collaborates across various related tools to provide a complete solution to customers. Possesses excellent communication and inter-personal skills.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Exp : 3- 5 Yrs Position : Senior or Lead Expertise : Power fundamentals Good knowledge of PTPX Good knowledge of CLP Knowledge of design verification, RTL coding, synthesis, and physical design Protocol knowledge of , DDR, CHI, Cache, computer organization, bus protocol, Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age and this is where you come in. Join QCOM Technologies Inc Global Emulation(Prototyping) team delivering solutions for design of leading-edge wireless products. Qualcomm is leading 5G innovations ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. The Qualcomm Global emulation team is currently seeking a lead engineer role for our team doing development/validation of large scale FPGA emulation tools/flows/methodologies In this role, you will be working in multiple areas of SoC/IP prototyping flows and methodologies. Would also involve enabling execution teams doing SOC prototyping during their usage of the platform Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 4-7 years of experience working in FPGA Synthesis, Prototyping of SoCs & IPs Candidates are expected to have experience in: Prior work experience on Emulation/Prototyping Platforms (HAPS, VPS, Protium etc) Multi-FPGA prototyping flow, from RTL preparation to h/w implementation Proficient in analysis & debug of issue in Synthesis, Place and Route, Timing closure, Clocking. Hands on experience in FPGA h/w debug using probes/ILA Proficient in EDA tools like - Vivado, Synplify, Protocompiler, VPS, VCS/Verdi etc RTL coding and simulation Well versed with working in unix/linux environment, using GVIM/VI editors, shell scripting Strong debug skills, aptitude to learn and resolve complex issues Experience in one or more scripting language - TCL, Python, Perl, Shell etc Sound knowledge of: FPGA architecture preferably Xilinx (ultrascale), Vivado IP catalog Synthesis, Timing concepts and SDC constraints Prototyping concepts like - partitioning, pinmux

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Additional Additional Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 6+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience. OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 5+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience. OR PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience. Preferred Qualifications: 10 years of experience Strong understanding of CAD/EDA tools and methodologies. Strong experience scripting (Python, Perl) in support of design verification Hands on experience with regression systems, CI/CD, Revision Control System (git, perforce) workflow. Strong fundamentals in digital design verification methodologies and EDA tools. Knowledge of SOC architecture Experience with web programming (javascript, etc) and databases. Principal Duties and Responsibilities: Develop and implement advanced CAD flows and methodologies to verify critical high performance and low power CPU designs. Utilize scripting languages (python) to automate CAD/IT processes and increase efficiency. Collaborate with cross-functional teams to ensure successful integration of CAD flows. Stay up-to-date with cutting-edge technology, conduct thorough analysis of CAD tools and make improvements. Work closely with users to troubleshoot and resolve any issues that arise in tools, flows, environment, and infrastructure. Collaborate with external vendors to ensure timely delivery, integration, and deployment of CAD/EDA tools while driving them to improve efficiency and productivity. Define and implement new infrastructure capabilities that can be used to accelerate design and development. Level of Responsibility: Works independently with minimal supervision. Work with chip leads in support of design verification. Collaborate with chip leads to understand the design methodology. high-level requirements, determine other areas to support current or future designs that can benefit from automation and tooling. Provides supervision/guidance to other team members. Decision-making is significant in nature and affects work beyond immediate work group. Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc. Has a moderate amount of influence over key organizational decisions. Tasks do not have defined steps; planning, problem-solving, and pri

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Job Overview In this highly cross functional role, you will be part of the Global Design Enablement team responsible for various aspects of PDK development across Custom, Analog and RF technology nodes. As a member of the CAD team, you will be working closely with Custom, Analog & RF Engineering design community to develop & support customized tools and flows for Schematic & Layout design, Circuit Simulation, IP characterization, Custom/Analog P&R and transistor-level EM/IR flows. You will also have the responsibility to collaborate with our Foundry and EDA partners to deploy best-in class EDA tools and flows in addition to developing in-house productivity & QoR automation solutions for improving overall design methodology. Minimum Qualifications Bachelors or masters in electrical engineering, Computer Science, or related field. 6+ years of industry experience in CAD/EDA or PDK development Knowledge of Virtuoso suite of tools- Schematic, Layout, Analog Design Environment etc. Proficiency in one or more of the programming/scripting languages- , Python, Perl and TCL. Good understanding of CMOS fundamentals and Circuit Design Concepts Strong aptitude for programming and automation Good communication skills and ability to work collaboratively in a team environment Preferred Qualifications Familiarity with SPICE simulation tools (Hspice, SpectreX/APS, AFS/Solido SPICE , PrimeSim SPICE, ADS, GoldenGate etc.) Experience with Electromagnetic tools, like Peakview and EMX, is a plus. Knowledge of FinFet & SOI processes is a plus Educational RequiredBachelor's, Electrical Engineering