160 Eda Tools Jobs - Page 4

Meet the Team The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry. Your Impact Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs. Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL. Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows. Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies. The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship. Minimum Qualifications: Bachelor's or a Masters Degree in Electrical or Computer Engineering required with at least 7+ years of experience. Knowledge of the latest innovative trends in DFT, test and silicon engineering. Background with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan. Background with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime Verification skills include, System Verilog Logic Equivalency checking and validating the Test-timing of the design Knowledge of the latest innovative trends in DFT, test and silicon engineering. Experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan. Prior experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime Prior experience working with Gate level simulation, debugging with VCS and other simulators. Prior experience with Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687 Prior experience with Scripting skills: Tcl, Python/Perl. Preferred Qualifications: Verilog design experience developing custom DFT logic & IP integration; familiarity with functional verification DFT CAD development Test Architecture, Methodology and Infrastructure Background in Test Static Timing Analysis Past experience with Post silicon validation using DFT patterns.

This is a full-time on-site role for an RTL Lead located in Bengaluru. You will be responsible for designing and implementing RTL code, verifying and validating designs, collaborating with hardware and software teams, and ensuring the achievement of project milestones. Additionally, you will be involved in reviewing design specifications, optimizing system performance, and troubleshooting as needed. Qualifications: - Experience in RTL Design, Verilog, VHDL - Proficiency in Simulation Tools and FPGA prototyping - Strong understanding of Digital Design, Logic Design, and Circuit Design - Knowledge of SoC Architecture and Integration - Proven experience with EDA tools like Synopsys, Cadence - Excellent problem-solving and analytical skills - Ability to work in a team and communicate effectively - Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field - Experience in the semiconductor industry is a plus If you are interested in this opportunity, kindly share your resume to mahadev@msmcad.com.,

cv shared to shilpa.srivastava@orcapod with Recruiter Semi conductor industry Role & responsibilities candidate should have experience in hiring for semi conductor industries screening of resumes sourcing of candidates

Who We Are The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. With ~2,100 employees across 16 countries, we design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry. Who You'll Work With You will be in the Silicon One development organization as an ASIC Implementation Technical Lead in Bangalore India with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a member of this team you will also be involved in crafting groundbreaking next generation networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases with additional exposure to physical design signoff activities. What You'll Do Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs. Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL. Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows. Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies. The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship. Who You Are You are an ASIC Design for Test Hardware Engineer with 10+ years of related work experience with a broad mix of technologies. Minimum Qualifications: Bachelor's or a Masters Degree in Electrical or Computer Engineering required with at least 10 years of experience. Knowledge of the latest innovative trends in DFT, test and silicon engineering. Experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan. Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime Verification skills include, System Verilog Logic Equivalency checking and validating the Test-timing of the design Knowledge of the latest innovative trends in DFT, test and silicon engineering. Experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan. Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime Experience working with Gate level simulation, debugging with VCS and other simulators. Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687 Strong verbal skills and ability to thrive in a multifaceted environment Scripting skills: Tcl, Python/Perl. Preferred Skills: Verilog design experience developing custom DFT logic & IP integration; familiarity with functional verification DFT CAD development Test Architecture, Methodology and Infrastructure Test Static Timing Analysis Post silicon validation using DFT patterns. Why Cisco #WeAreCisco, where each person is unique, but we bring our talents to work as a team and make a difference powering an inclusive future for all. We embrace digital, and help our customers implement change in their digital businesses. Some may think were "old" (36 years strong) and only about hardware, but were also a software company. And a security company. We even invented an intuitive network that adapts, predicts, learns and protects. No other company can do what we do - you cant put us in a box! But "Digital Transformation" is an empty buzz phrase without a culture that allows for innovation, creativity, and yes, even failure (if you learn from it). Day to day, we focus on the give and take. We give our best, give our egos a break, and give of ourselves (because giving back is built into our DNA.) We take accountability, bold steps, and take difference to heart. Because without diversity of thought and a dedication to equality for all, there is no moving forward. So, you have colorful hair Dont care. Tattoos Show off your ink. Like polka dots Thats cool. Pop culture geek Many of us are. Passion for technology and world changing Be you, with us!,

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe , CXL , and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com . Basic Qualifications : Bachelor s degree in electrical engineering (EE) is required; a master s or PhD in EE is preferred. Additional background in Math or Computer Science is highly desirable. 8+ years of experience in formal verification or 7+ years of experience in traditional design verification (DV). Strong professional work ethic with the ability to manage and prioritize multiple tasks in a dynamic environment. Proven ability to plan and prepare for customer meetings and to work with minimal supervision. Entrepreneurial mindset with a proactive, customer-focused attitude. Ability to think and act quickly while maintaining a high standard of quality. Strong cross-functional collaboration skills. Required Experience : Develop detailed formal verification (FV) test plans based on design specifications and collaborate with design teams to refine micro-architecture specifications. Identify key logic components and critical micro-architectural properties essential for ensuring design correctness. Implement formal verification models, abstractions, assertions, and utilize assertion-based model checking to detect corner-case bugs. Apply complexity reduction techniques using industry-standard EDA tools or academic formal verification tools to achieve proof convergence or sufficient depth. Develop and maintain scripts to enhance FV productivity and streamline verification processes. Assist design teams with the implementation of assertions and formal verification testbenches for RTL at unit/block levels. Participate in design reviews and collaborate with design teams to optimize design quality and performance, power, area (PPA) metrics based on formal analysis feedback. Strong proficiency in System Verilog/Verilog. Good scripting abilities with Python or Perl. Preferred Experience : Hands-on experience with formal verification tools such as Synopsys VCFormal and Cadence JasperGold. Experience with both bug hunting and static proof verification techniques. Familiarity with automating formal verification workflows within a CI/CD environment. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

We are hiring a strong Design Verification (DV) engineer. This opening is with our CPU Design Verification team. This role is for you if you are curious about Computer organisation and design, and possess strong digital design fundamentals. This role is with a Hardware design and verification team that develops and builds chips enabling the AI revolution. What you will be doing: You will own and develop verification components, such as checkers, models, coverage, and stimulus. You will work closely with the Architecture, RTL, and Formal Verification teams to design and verify the microarchitecture. You will propose methodology, tests and frameworks to ensure bug-free RTL. You will participate in Design specification reviews, architecture reviews, and reviews of other unit test plans. Build DV code and Algorithms that are of high quality, with excellent time and space complexity, that scale well to higher testbenches. You will actively work on understanding the ARM architecture and coherency protocols, such as CHI. You will learn the microarchitectures of the interconnect, cache, ordering, and memory units in the system. This role will enable you to develop expertise in CPU load/store, MMU, caching, coherency/consistency, fabric, and related areas. You will design and verify the next generation of NVIDIA CPUs and SoCs! What we need to see: BS or MS in Electronics Engineering with a minimum of 3+ years of proven experience Knowledge in Design Verification Methodologies SV/UVM verification languages and methodologies. Strong problem solving - more specifically, DV code like stimulus, models, constraints, coverage Prior experience in Testbench architecture and Verification components A strong understanding of CPU architecture and microarchitecture Way to stand out from the crowd: Understanding CPU Architecture concepts related to load/store, caching, coherency, consistency and ordering Strong Python and other software methodologies for scripting and build automation Experience in handling EDA tools from Synopsys or Cadence With competitive salaries and a generous benefits package, we are widely considered as one of the technology world s most desirable employers. We have some of the most dedicated and experienced professionals in the world working for us, and, due to unprecedented growth, our elite engineering teams are expanding rapidly. If youre a creative and autonomous engineer with a real passion for technology, we want to hear from you! We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, colour, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status. #LI-Hybrid

Key Responsibilities: Define and lead the strategy for VLSI front-end design services Build and scale high-performing VLSI engineering teams (from 50 to 500+) Engage with customer design managers and secure design wins through deep technical collaboration Mentor and upskill engineering teams in line with evolving industry needs Ensure successful delivery of ASIC design and verification projects Develop innovative proposals and drive new project wins Collaborate with internal resourcing teams and external partners to fulfill staffing needs Represent VLSI practice in industry forums and events Must-Have Skills: Strong leadership experience in VLSI/ASIC front-end engineering Expertise in RTL design, UVM-based verification, UPF/SDC, formal verification, emulation Hands-on with commercial EDA tools (Synopsys, Cadence, Siemens) Familiarity with Verilog and standard formats (LEF/DEF/SPEF) Client engagement, delivery management, and proposal leadership Good-to-Have Skills: Industry connects with EDA vendors, foundries, and Tier-1 semiconductor companies Knowledge of ASIC-package co-design Experience in defining VLSI roadmaps, SoW/MSA processes Automation exposure (Python/Perl) Awareness of semiconductor industry trends and competitor insights

Key Responsibilities: Define and lead VLSI back-end services strategy and offerings Build and scale high-performing VLSI engineering teams (300+ roadmap) Engage with semiconductor clients for technical discussions and project wins Oversee delivery of back-end services including physical design, STA, DFT, timing/power analysis Collaborate with sales, presales, and partner ecosystem to drive business growth Mentor engineers and ensure alignment to latest tech trends and client needs Lead proposal creation, solution demos, and client engagement at senior levels Must-Have Skills: Strong experience in VLSI/ASIC back-end engineering Physical design, timing closure, DFT, power/performance optimization Expertise in EDA tools (Synopsys, Cadence, Siemens) Verilog, LEF/DEF/SPEF formats Excellent leadership, communication & stakeholder management Good-to-Have Skills: Proficiency in scripting (Python, Perl, Tcl) Experience with advanced node technologies (7nm, 5nm, etc.) Exposure to ASIC-package co-design Strong industry connects (EDA vendors, foundries, Tier-1 chipmakers) Strategy planning, SoW/MSA reviews, innovation initiatives

Looking for the Mechanical Engineer, who have good experience in 3D cable routing modeling by using NX (proficient) / Creo (good). SCOPE OF WORK: Requires knowledge and experience in own discipline (Mechanical design and 3D routing modeling) Design or modify mechanical engineering layouts/schematics and/or detailed drawings/specifications of moderate scope under general supervision Perform and document engineering tests under general supervision Troubleshoot a variety of mechanical problems of moderate difficultly under general supervision Implement concepts of moderate product issues and mechanical solutions of moderate difficulty May be responsible for the design, development and implementation of custom mechanical tooling, fixturing, and associated processes to enable the handling, assembly and/or disassembly of parts, components, sub-assemblies and final assemblies throughout the product life cycle Solves problems in straightforward situations; analyzes possible solutions using technical experience and judgment and precedents Demonstrates expanded conceptual knowledge in own discipline and broadens capabilities Impacts quality of own work and the work of others on the team; works within guidelines and policies WORK REQUIREMENTS Support required to create Cable routing using using UG/NX. Creo routing experience: ~2-3 continuous years UG/NX routing : ~ Communication: Good communication (English) with global stake holders Qualification : BE (Engineering)

Need to work in collaboration with global analog teams across sites. Will be responsible for driving innovation in Analog IP designs. Responsible for design of IPs like Voltage regulators, LDO, Current and Voltage reference, High Voltage charge pumps, temperature sensors, oscillators etc using industry standard EDA tools. Should provide technical leadership and mentor junior engineers. Responsible for developing processes and robust design methodology. Help build overall competency in Analog domain. Qualifications Bachelor or Master Degree in Electrical/Electronic Engineering with 12+ years of experience in Analog design across different technologies. Should have experience in developing analog IPs like Switc

We are hiring a CAD Automation Software Engineer (Frontend & Backend) with 10+ years of experience to deploy and support front-end tools, develop scripts for regression and debug flows, and collaborate with design, implementation, and verification teams. The candidate must be proficient in scripting (Python, Bash, C), Linux administration, and version control (Git/Mercurial). Experience in ASIC flows, CAD tools, and CI/CD setup is essential.

Sr DFT Engineers and Managers - location remote any where in India Job Summary Our clients Arasan Chip Systems (www.arasan.com) based in US are seeking for their India Development Center Senior and Experienced DFT Engineer with 68 years of hands-on expertise in Design-for-Test methodologies and implementation for complex SoC designs. The candidate will be responsible for developing and integrating DFT architectures, driving ATPG and MBIST flows, and working closely with RTL design, physical design, and test teams to ensure high test coverage and silicon readiness. Key Responsibilities Define and implement DFT architecture for digital IP and SoCs. Insert and verify scan chains, boundary scan (JTAG), and test points. Develop and run ATPG and MBIST for various memory instances. Generate and validate test patterns (stuck-at, transition, path delay). Collaborate with RTL, synthesis, and physical design teams to ensure DFT integration and timing closure. Participate in silicon bring-up and ATE support. Support internal reviews, audits, and DFT documentation. Skills Strong experience with industry-standard DFT tools (Mentor Tessent, Synopsys DFTMAX, Cadence Modus, etc.). Hands-on experience in scan insertion, ATPG, MBIST, boundary scan, and test compression techniques. Familiarity with ATE pattern generation and silicon debug flows. Solid understanding of RTL/gate-level simulation, synthesis, STA, and timing-aware DFT flows. Proficiency in scripting languages (TCL, Perl, Python) for automation. Excellent analytical and problem-solving skills. Qualifications B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or related field. 6–8 years of relevant experience in DFT for ASIC/SoC design. Preferred Exposure to low-power DFT methodologies (UPF/CPF flows). Prior experience with automotive or high-speed PHY IP integration is a plus. Knowledge of IEEE standards (1149.1, 1500, 1687).

Title: Standard Cell Layout Design About GLOBALFOUNDRIES GLOBALFOUNDRIES is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world s most inspired technology companies. With a global manufacturing footprint spanning three continents, GLOBALFOUNDRIES makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com . Introduction In this position you will be integrated in our Foundry IP Development team in Bangalore. In close collaboration with other disciplines across our worldwide engineering teams you will be developing layout for Std cell IP which enable our customers to perform product designs at highest quality standards based on Globalfoundries advanced process nodes. Job Responsibilities The development of product grade Standard Cell IP covering the following phases: Layout Design of Standard Cell IPs Layout checks like LVS, DRC, DFM, EMIR Review of Layouts and extend help for other Layout teams Design Kit prep from layout side, verification and validation Layout automation and script support Being a good team player, taking key initiatives for productivity improvements and innovation Sign off and release into dedicated IP validation test chips Specification and documentation Support of silicon bring up and characterization Required Qualifications: Bachelor s degree with 10+ years or master s degree with 8+ years experience in semiconductors / Microelectronics / VLSI engineering. Practical experiences in Standard Cell layout design in one or several of the following areas: Layout design and optimization of Combinational and Sequential Cells for various drive strengths and topology options. Layout design of Power Management Kit cells like Level Shifter, Power Gating, Isolation and Always-on Cells. Layout Architecture design for Ultra High Density and High-Performance Libraries. Layout design of custom cells to meet specific low power or high-speed design requirements. Proficient in handling EDA tools from Synopsis, Mentor and Cadence used for layout design like schematic/layout editor, parasitic extraction tools, DRC, LVS, DFM, EMIR, etc. Basic understanding of fabrication steps and flow. Experience in Testchip integration and analysis will be an added advantage. Preferred Qualifications: Good knowledge of CMOS technology Hands-on knowledge of state-of-the-art standard cell layout flows Programming experience applicable to design flow automation tasks The ability to work within a very dynamic interdisciplinary environment as well as dedicated knowledge of 45/32/28nm and below technology nodes are an advantage. You are flexible, highly motivated and have a team-oriented working style. You have shown the ability to communicate as well as work efficiently in an international multi-disciplinary environment. Strong written and verbal communication skills in English are a must.

Title: Standard Cell Layout Design About GLOBALFOUNDRIES GLOBALFOUNDRIES is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world s most inspired technology companies. With a global manufacturing footprint spanning three continents, GLOBALFOUNDRIES makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com . Introduction In this position you will be integrated in our Foundry IP Development team in Bangalore. In close collaboration with other disciplines across our worldwide engineering teams you will be developing layout for Std cell IP which enable our customers to perform product designs at highest quality standards based on Globalfoundries advanced process nodes. Job Responsibilities The development of product grade Standard Cell IP covering the following phases: Layout Design of Standard Cell IPs Layout checks like LVS, DRC, DFM, EMIR Review of Layouts and extend help for other Layout teams Design Kit prep from layout side, verification and validation Layout automation and script support Being a good team player, taking key initiatives for productivity improvements and innovation Sign off and release into dedicated IP validation test chips Specification and documentation Support of silicon bring up and characterization Required Qualifications: Bachelor s degree with 10+ years or master s degree with 8+ years experience in semiconductors / Microelectronics / VLSI engineering. Practical experiences in Standard Cell layout design in one or several of the following areas: Layout design and optimization of Combinational and Sequential Cells for various drive strengths and topology options. Layout design of Power Management Kit cells like Level Shifter, Power Gating, Isolation and Always-on Cells. Layout Architecture design for Ultra High Density and High-Performance Libraries. Layout design of custom cells to meet specific low power or high-speed design requirements. Proficient in handling EDA tools from Synopsis, Mentor and Cadence used for layout design like schematic/layout editor, parasitic extraction tools, DRC, LVS, DFM, EMIR, etc. Basic understanding of fabrication steps and flow. Experience in Testchip integration and analysis will be an added advantage. Preferred Qualifications: Good knowledge of CMOS technology Hands-on knowledge of state-of-the-art standard cell layout flows Programming experience applicable to design flow automation tasks The ability to work within a very dynamic interdisciplinary environment as well as dedicated knowledge of 45/32/28nm and below technology nodes are an advantage. You are flexible, highly motivated and have a team-oriented working style. You have shown the ability to communicate as well as work efficiently in an international multi-disciplinary environment. Strong written and verbal communication skills in English are a must. GlobalFoundries is an equal opportunity employer, cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity, efficiency and innovation whilst our employees feel truly respected, valued and heard. As an affirmative employer, all qualified applicants are considered for employment regardless of age, ethnicity, marital status, citizenship, race, religion, political affiliation, gender, sexual orientation and medical and/or physical abilities. All offers of employment with GlobalFoundries are conditioned upon the successful completion of background checks, medical screenings as applicable and subject to the respective local laws and regulations.

Need to work in collaboration with global design teams across sites. Will be responsible for driving innovation in Analog IP designs. Responsible for design of IPs like Switched capacitor circuits , Voltage regulators, LDO, Current and Voltage reference, High Voltage charge pumps, temperature sensors, oscillators etc using industry standard EDA tools. Should provide technical leadership and mentor junior engineers. Responsible for developing processes and robust design methodology. Help build overall competency in Analog domain. Qualifications Bachelors/ Masters degree in Electrical/ Electronics Engineering with 8+ years of experience in Analog Circuit Design across different technologies. Should have experience in developing analog IPs li

Responsibilities Understand the standards/specifications Architecture development and documenting implementation level details Hands on work for every aspect of verification cycle Responsible for the compliance with the latest Methodologies. Developing Verification IPs Define Functional Coverage matrix and Comprehensive Test plan Regression management and functional coverage closure DUT integration and verification for IP delivery sign-off Leading small team Person Specification Required Skills Hands-on experience of complete verification cycle with strong verification concepts Strong knowledge of Verilog, SystemVerilog and UVM Experience in UVM based Verification IP development Experience in AMBA AXI/AHB/APB System buses Hands on work experience on any of PCIe/Eth/USB/DDR etc. Hands on experience with System Verilog Assertions Scripting for automation, release process, simulations, regressions Good command over written and oral communication Desirable Skills Lead the Verification IP development with 2 or more junior engineers Exposure to full verification cycle Desired Skills and Experience DV Engineer, Design Verification, Verification Engineer

Looking for Platform/Board Design Engineers with the following requirements and this is an immediate requirement. Extensive experience in hardware board design. Strong foundation and expertise in analyzing digital, Analog and power electronic circuits. Proficient with AMD FPGAs, CPLD and MPSOC architecture-based board designs. Knowledgeable in signal integrity, EMI/EMC concepts for digital and power electronics. Completed at least one project from high-level design to final product level validation. Capable of independently handling schematic Capturing, design analysis DC Drop, Singal Integrity, and coordinating reviews with peer of layout, mechanical, SI, and EMC teams. Experienced in board bring-up, issue investigation, and triage in collaboration with firmware and software teams. Skilled in preparing hardware design documentation, validation test planning, identify necessary test equipment, test development, execution, debugging, and report preparation. Effective communication and interpersonal skills for collaborative work with cross-functional teams, including post-silicon bench validation, BIOS, and driver development/QA. Experience with server platforms and ATX-based complex HDI board designs s is a plus. Hands-on experience with Cadence Allegro/Altium EDA tools is essential. Familiarity with programming and scripting languages like Python and Perl, and experience in test automation is advantageous. Education Requirements: B. Tech/B.E./M. Tech/M.E. Experience: 5 to 10 Years Location: Hyderabad Shift: 9:30 AM to 6:30 PM Work Mode: Office (Monday to Friday)

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: In this role, the Engineer will apply and lead Broadcoms proven design methodology and milestone flow to meet Broadcoms rigorous criteria for achieving Right-first time silicon. Candidate should have very good experience in layout activities of block and level. Should be well experienced in floor-planning, partitioning, placement, clock tree synthesis, route and physical verification. Responsibilities include, but not limited to: Understanding of SoC for top-down/bottom-up physical design integration in 5nm and lower technologies Must have deep functional knowledge of P&R flows, should be able to catch up quickly on internal flows, adapt. Implement timing and functional ECO P&R, Extraction, Physical verification, work towards STA closure Build automation flows wherever needed/adapt to existing flows for re-use Must be proficient in any of the Cadence/Synospys/Mentor EDA tools for P&R, PV, STA, ECO Needs to be automation savvy with high expertise in one of the programming languages used in the industry Clearly know requisites for executing his/her job and lead by example Bring tangible improvement in TAT with better quality Minimum Qualifications: MSEE/MSCS 3+ years (BSEE/BSCS 5+ years) A deep understanding of backend digital design flow Proficient in timing constraints, physical constraints Proficient in handling EDA tools across floorplan / partition / placement / cts / route stages for SoC TOP. Proficient with backend EDA tools viz, Genus/Innovus/Quantus/Tempus, DC/Star-RCXT/PT, PrimeRail/Voltus, Redhawk Proficiency in Tcl and Perl Excellent analytical skills Shown ability to collaborate in a multi-functional environment, cross-site or cross-time zone .

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: In this role, the Engineer will apply and lead Broadcoms proven design methodology and milestone flow to meet Broadcoms rigorous criteria for achieving Right-first time silicon. Candidate should have very good experience in layout activities of block and level. Should be well experienced in floor-planning, partitioning, placement, clock tree synthesis, route and physical verification. Responsibilities include, but not limited to: Understanding of SoC for top-down/bottom-up physical design integration in 5nm and lower technologies Must have deep functional knowledge of P&R flows, should be able to catch up quickly on internal flows, adapt. Implement timing and functional ECO P&R, Extraction, Physical verification, work towards STA closure Build automation flows wherever needed/adapt to existing flows for re-use Must be proficient in any of the Cadence/Synospys/Mentor EDA tools for P&R, PV, STA, ECO Needs to be automation savvy with high expertise in one of the programming languages used in the industry Clearly know requisites for executing his/her job and lead by example Bring tangible improvement in TAT with better quality Minimum Qualifications: MSEE/MSCS 3+ years (BSEE/BSCS 5+ years) A deep understanding of backend digital design flow Proficient in timing constraints, physical constraints Proficient in handling EDA tools across floorplan / partition / placement / cts / route stages for SoC TOP. Proficient with backend EDA tools viz, Genus/Innovus/Quantus/Tempus, DC/Star-RCXT/PT, PrimeRail/Voltus, Redhawk Proficiency in Tcl and Perl Excellent analytical skills Shown ability to collaborate in a multi-functional environment, cross-site or cross-time zone

We are hiring a CAD Automation Software Engineer (Frontend & Backend) with 10+ years of experience to deploy and support front-end tools, develop scripts for regression and debug flows, and collaborate with design, implementation, and verification teams. The candidate must be proficient in scripting (Python, Bash, C), Linux administration, and version control (Git/Mercurial). Experience in ASIC flows, CAD tools, and CI/CD setup is essential.

Need to work in collaboration with global design teams across sites. Will be responsible for driving innovation in Analog IP designs. Responsible for design of IPs like Switched capacitor circuits , Voltage regulators, LDO, Current and Voltage reference, High Voltage charge pumps, temperature sensors, oscillators etc using industry standard EDA tools. Should provide technical leadership and mentor junior engineers. Responsible for developing processes and robust design methodology. Help build overall competency in Analog domain. Qualifications Bachelors/ Masters degree in Electrical/ Electronics Engineering with 8+ years of experience in Analog Circuit Design across different technologies. Should have experience in developing analog IPs like Switch capacitor circuits, LDO, DC-DC convertor, oscillator, ADCs, Should have experience in integrating Analog IPs in a complex system. Knowledge of PCB and system design will be preferred. Should experience in silicon characterization and probing. Should have experience in a multi-site environment, interacting with teams in other sites. Should possess good mentorship skills. Ability to coordinate priorities and initiatives

Strong program management skill design and development of Automotive Interior Body Trims IP console. Experience in A, B, C pillar trims, Dashboard assembly, Front and Rear Door Trims, Center Console, Side panels Trims, head liner, Sunroof. Having god experience in Floor carpet, Headliners, NVH.

Strong program management skill Upper Body, Underbody, Closure, Surfacing, Sheet metal manufacturing, stamping feasibility. A class surface, mastersurface preparation, style feasibility, Body structure, Outer panel, inner panel, reinforcements, doors.

Strong program management skill with a goal/target minded discipline process excellent communication and interpersonal skills. Experience in Exterior Body trims such as front body bumper, Grill, Side cladding, Wheel arch, Rear bumper, Mudflap

Job Description Position: - Sales Engineer Qualification: BE/ B Tech. in Electronics Experience: 2- 5 Years Location: Delhi/Hyderabad/Pune/Kolkata No. of positions: 10 The Sales Engineer is a customer facing role, responsible for the complete sales process - demand creation, mapping of accounts and closure. The candidate should be able to effectively communicate EDA / MCAD product capabilities and the benefits of the solutions through presentations and sales demonstrations. Conduct discovery and requirements gathering sessions to analyze and understand customer needs, workflows and technical requirements. Develop and/or collate sample documents, applications and other sales enablement materials for use during the sales and marketing sessions. Collaborate with Technical and services teams to specify, recommend and architect comprehensive customer solutions Required Skills : Relevant Sales experience in Defense / Institutional Sales /Private Commercial Sales/Academics Sales experience in Application or Engineering Software Knowledge on EDA tools Siemens EDA / Cadence / Synopsys Knowledge on MCAD tools Cero (ProE)/UGNX/Catia/Solid edge/Solid works/Inventor Knowledge on CAE Tools Ansys/Nastran/Adams/Altair Knowledge of Procurement procedures such as Tender, Gem portal, E-tender, etc. Must be aware about the complete sales cycle Responsibilities: Identify customer needs and recommend suitable products/solutions Deliver product/concept presentations and conduct industry seminars Resolve client queries and manage sales concerns Capable of analyzing the merit of opportunities Skilled in identifying customer pain points Soft Skills: Team-oriented with strong analytical and presentation skills Creative, confident, and proactive Able to perform under pressure and meet targets Culturally adaptable with strong convincing skills Willing to travel extensively (7075%)