86 Eda Tools Jobs - Page 3

Staff Engineer, Analog Location: Bangalore Key Responsibilities Developing low-power, high-performance analog circuits, including OpAmp, Comparators, Bandgap References, LDOs, Capless LDO, ADCs, DACs, PLL, DLL, Switching Regulator, High Speed IOs, DDR in advanced process nodes. Defining circuit implementation architecture based on specifications, creating transistor-level designs, and collaborating with analog layout designers for optimization. Creating and maintaining documentation for designs, including specifications, test plans, usage guidelines, and limitations. Collaborating with system architects, the analog design team, and the DV (Design Verification) team for DV modeling and digital top verification. Mentoring junior designers and sharing best practices to enhance design performance and productivity. Requirements : B. Tech /BE/ME/M Tech in Electronics/Electrical Engineering or related fields with 5+ years of relevant hands-on experience. Strong experience in analog and mixed-signal circuit design and/or architecture. Experience with advanced process/FinFET is a plus. Understanding of device basics and physics, with an understanding of the following: High speed Driver and Receiver designs, PLL design with solid system understanding Hands-on experience of Sub block design of Current mirrors, bandgap reference, Opamp, amplifiers with small-signal analysis of several topologies. Experience in ADC/DAC/Regulator or High Speed SerDes circuit design Good knowledge of devices, circuits, and EDA tools (schematic, layout, simulator, RC extraction, etc.), considering trade-offs among performance, power consumption, die area, and reliability. Basic knowledge of the following layouts: antenna checks, antenna failure, latchup issues, ESD constraints, and layout rules, ERC related checks, matching, cross talk, coupling, shielding, guard ring usage, LEF generation, .lib characterization, extraction setup, DRC LVS runs switch knowledge, IR drop requirements, EM issues, parasitic matching, parasitic reduction techniques, and static and dynamic IR analysis Self-motivated team player with strong problem-solving skills to collaborate with various teams to achieve desired goals. Excellent written and verbal communication skills.

Design and development of CV, Steering and front axle aggregates knowledge Bus and load platform Casting and forging manufacturing processes knowledge, DMEA, DFA, DFS, DFM. Knowledge of DVP, 6 Hands on experience in CATIA. Ability to resolve the problems, Basic knowledge of vehicle dynamics ADAMs, MBD. Knowledge of Homologation requirements.

CV vehicles rear axle, propeller shaft, wheels and tyres aggregates knowledge, 2. basic manufacturing processes knowledge, DMEA, DFA, DFS, DFM. Good Knowledge in joinery design, Bolted, Knowledge of homologation requirements, Knowledge of DVP, Hands on experience in CATIA. Ability to resolve the problems,

CV vehicles suspension and lift axle along with mounting aggregates knowledge, Sheet metal, casting, forging manufacturing processes knowledge, DMEA, DFA, DFS, DFM. Good Knowledge in joinery design, Knowledge of DVP, Hands on experience in CATIA. Ability to resolve the problems

Education : Bachelors in mechanical engineering Must have skills: Mechanical background, Engineering fundamental, Microsoft project plan (MPP), Excellent communication and teamwork abilities, Excellent verbal skills Experience on: Basic product lifecycle management knowledge. Proven experience in mechanical project management. Proficiency in CAD, FEA, and project management tools. Strong leadership and problem-solving skills. Knowledge of industry standards (ASME, ISO, etc.) Responsibilities: Manage and oversee mechanical projects from start to finish. Ensure projects are completed within budget, on time, and to the highest quality standards. Coordinate with clients, contractors, and other stakeholders to ensure project requirements are met. Develop and maintain project schedules and budgets using MS Project Plan. Conduct reviews to ensure work is progressing according to plan. Manage project documentation and ensure accurate record-keeping. Provide regular project status updates to senior management.

Responsibilities may be quite diverse of a technical nature. U.S. experience and education requirements will vary significantly depending on the unique needs of the job. Job assignments are usually for the summer or for short periods during breaks from school. Qualifications Mtech graduate with below skillsHardware : VLSI Design, Custom Layout, ESD verification Software : Python, perl Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

About The Role Designs, develops, and builds analog circuits in advanced process nodes for analog and mixed signal IPs.Designs floorplans, performs circuit design, extracts chip parameters, and simulates analog behavior models.Creates test plans to verify design according to circuit and block microarchitecture specifications and evaluates test results.Verifies functionality to optimize circuit for power, performance, area, timing, and yield goals.Collaborates cross functionally to report design progress and collects, tracks, and resolves any performance and circuit design issues.Optimizes performance, power, area, and reduces leakage of circuits. Works with architecture and layout team to design circuit for best functionality, robustness, and electrical capabilities. Qualifications Qualifications:B.Tech with 3+ years or M.Tech with 2+ Years of hands-on experience in high-speed analog circuit design, with a proven track record of successful projects.Expertise in designing and verifying analog circuits such as High-speed transmitter, recevier, amplifiers, PLLs, voltage regulators, and data converters.Proficiency in using EDA tools like Cadence Virtuoso, SPICE, or Synopsys. Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

About The Role Come join Intel's highly regarded Devices Development Group, responsible for creating Client SOCs. We envision the future of computing and design for the next generation of laptop and desktop computers. We are looking for a SoC Physical Design Engineer, who is ready to research, design, develop, and test lead Intel designs as we reimagine how to build SoCs at Intel and in the semiconductor industry. Our bold purpose as a company is to create world-changing technology that enriches the lives of every person on earth and this role is instrumental in furthering our mission to shape the future of technology. Your responsibilities may include but not be limited to: Performing physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Physical Synthesis, Floor planning, Place and Route, Clock Tree Synthesis with Synopsys and/or Cadence EDA tools. Multiple Power Domain analysis and handling using standard Power Formats UPF or CPF. Verification and Signoff including Formal Equivalence Verification, Static Timing Analysis, Reliability Verification, Static and Dynamic power integrity, Layout Verification, Electrical rule checking, Noise analysis and Structural Design checking. Analyzes results and makes recommendations to fix violations for current and future product architecture. Participating in the development and improvement of physical design methodologies and flow automation. Driving performance optimization, including co-optimization, work with process teams, to create best-in-class designs. The ideal candidate should exhibit behavioral traits that indicate: Self-motivator with strong problem-solving skills. Excellent interpersonal skills, including written, verbal, and presentation communications. Attention to detail and organizational skills. Ability to work as part of a team and collaborate in a high-paced atmosphere. Qualifications BS/BTech degree with 12 years of experience, or MS/MTech degree with 10 years of experience, in Electronics Computer Engineering, or a related field. Preferred Qualifications: At least 10+ years of experience in physical design using industry EDA tools. Experience in Python/Perl/TCL programming languages Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

About The Role Come join Intel's highly regarded Devices Development Group, responsible for creating Client SOCs. We envision the future of computing and design for the next generation of laptop and desktop computers. We are looking for a SoC Physical Design Engineer, who is ready to research, design, develop, and test lead Intel designs as we reimagine how to build SoCs at Intel and in the semiconductor industry. Our bold purpose as a company is to create world-changing technology that enriches the lives of every person on earth and this role is instrumental in furthering our mission to shape the future of technology. Your responsibilities may include but not be limited to: Performing physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing. Physical Synthesis, Floor planning, Place and Route, Clock Tree Synthesis with Synopsys and/or Cadence EDA tools. Multiple Power Domain analysis and handling using standard Power Formats UPF or CPF. Verification and Signoff including Formal Equivalence Verification, Static Timing Analysis, Reliability Verification, Static and Dynamic power integrity, Layout Verification, Electrical rule checking, Noise analysis and Structural Design checking. Analyzes results and makes recommendations to fix violations for current and future product architecture. Participating in the development and improvement of physical design methodologies and flow automation. Driving performance optimization, including co-optimization, work with process teams, to create best-in-class designs. The ideal candidate should exhibit behavioral traits that indicate: Self-motivator with strong problem-solving skills. Excellent interpersonal skills, including written, verbal, and presentation communications. Attention to detail and organizational skills. Ability to work as part of a team and collaborate in a high-paced atmosphere. Qualifications BS/BTech degree with 8 years of experience, or MS/MTech degree with 6 years of experience, in Electronics Computer Engineering, or a related field. Preferred Qualifications: At least 8+ years of experience in physical design using industry EDA tools. Experience in Python/Perl/TCL programming languages Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

PREFERRED EXPERIENCE: • Minimum of 4-6 years' experience • Worked with EDA tools that enable RTL quality checks • Experience with analyzing the STA timing reports and identifying both the design and constraints related issues. • Ability to multitask, ramp up quickly on new flows/tools/ideas. • Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail etc. - other EDA tool experience acceptable Notice Period - 0 to 45 Days REQUIREMENTS: Attention to the detail Very good communication skills (both written and verbal) Fast learner and self-starter. Need to execute our custom regression scripts/quality checks for our complex designs (Multimode, multimillion gates and multiple partitions) Understand the PT/DC checks and review the reports to help clean up in order to meet each milestone targets Summarize the regression results periodically to track the progress. Able to debug the basic issues like SDC loading errors, check timing (no clock, unconstrained, no_clock, QoR violations)

Summary of Role: GlobalFoundries is seeking a highly motivated OPC/ORC Engineer to become part of the OPC team. This technical individual contributor will beresponsible for supporting GlobalFoundries advanced technology Optical Proximity Correction (OPC) and Optical Rule Check (ORC). Working on the leading edge technologies will provide an opportunity to develop new methodologies and business practices aimed at a highly efficient and world-class Data Prep operations. This position will be based in BLR, INDIA. Your Job: Develop and maintain OPC code (recipe) for various technodes Develop and maintain ORC code (recipe) for various technodes Work on different aspects of OPC code - like SRAFs, MRC, Booleans Do ORC review with required details and complete within agreed time Develop and maintain OPC code (recipe) for various technodes (like 12/14nm) supporting world wide fabs Develop and maintain ORC code (recipe) for various technodes (like 12/14>) supporting world wide fabs Work on different aspects of OPC code - like SRAFs, MRC, Booleans Do ORC review with required details and complete within agreed time Ability to work in a dynamic collaborative environment which requires strong teaming skills with Engineers, Technicians, Managers, and IT Interact with other GF Teams such as Fab Litho, Frame and Fab Integration Engineers to provide feedback to Release for D2M Reviews Disposition Ability to solve complex technical problems and contribute to multiple projects at the same time Strong ability to learn and explore new technologies, opportunities, and continuous improvement Familiarity with Fab processing is preferred Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety Security requirements and programs Required Qualifications: MS/MTech +internship is preferred Specialization on Microelectronics/VLSI or related fields Fluency in English Language - written verbal Basic coding familiarity Exposure to Mentor graphics EDA tools and/or SVRF language Familiarity with perl or tcl or python or shell is a plus. Familiarity with OPC is a big plus GlobalFoundries is an equal opportunity employer, cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity, efficiency, and innovation whilst our employees feel truly respected, valued and heard. As an affirmative employer, all qualified applicants are considered for employment regardless of age, ethnicity, marital status, citizenship, race, religion, political affiliation, gender, sexual orientation and medical and/or physical abilities. All offers of employment with GlobalFoundries are conditioned upon the successful completion of background checks, medical screenings as applicable and subject to the respective local laws and regulations. Information about our benefits you can find here: https: / / gf.com / about-us / careers / opportunities-asia

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Additional About The Role : General Summary We"™re looking for a frontend CAD developer to produce scalable software solutions for in-house EDA flows. As part of a cross-functional team, you"™ll be responsible for the full software development life cycle, from conception to deployment. Must have hands-on experience in developing the large software systems with structured development cycles. Should have good problem-solving skills, strong communication skills and a flair to work in a challenging environment Education B.E/B.Tech or M.E/M.Tech in VLSI/EE/EC/Computer Science Skills/Experience: 8 years of experience in EDA Tool/Flow Development, Deployment and Support Strong experience in Scripting languages like Perl, Tcl, Python, GUI development on Linux platform Should be well versed with VLSI frontend Design/Verification steps, RTL/System Verilog and UVM methodologies Knowledge of Clearcase Perforce, GIT, Makefiles Database design, Computer Architecture is a plus Desirable Scripting and automation skills:Unix/Linux shell programming, Perl/Python, Makefile Should be sincere, fast learner, committed, having good communication skills, and willing to take up new challenge

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Exp : 3 "“ 5 Yrs Position : Senior or Lead Expertise : Power fundamentals Good knowledge of PTPX Good knowledge of CLP Knowledge of design verification, RTL coding, synthesis, and physical design Protocol knowledge of , DDR, CHI, Cache, computer organization, bus protocol, Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. General Summary We"™re looking for a frontend CAD developer to produce scalable software solutions for in-house EDA flows. As part of a cross-functional team, you"™ll be responsible for the full software development life cycle, from conception to deployment. Must have hands-on experience in developing the large software systems with structured development cycles. Should have good problem-solving skills, strong communication skills and a flair to work in a challenging environment Education B.E/B.Tech or M.E/M.Tech in VLSI/EE/EC/Computer Science Skills/Experience: 8 years of experience in EDA Tool/Flow Development, Deployment and Support Strong experience in Scripting languages like Perl, Tcl, Python, GUI development on Linux platform Should be well versed with VLSI frontend Design/Verification steps, RTL/System Verilog and UVM methodologies Knowledge of Clearcase Perforce, GIT, Makefiles Database design, Computer Architecture is a plus Desirable Scripting and automation skills:Unix/Linux shell programming, Perl/Python, Makefile Should be sincere, fast learner, committed, having good communication skills, and willing to take up new challenges

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life s work , to amplify human creativity and intelligence. As an NVIDIAN, you ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! We are looking for a Senior Digital/Memory Mask Design Engineer - someone who is excited to join a growing group of diverse individuals responsible for handling challenging high-speed digital memory circuit designs. What youll be doing: Implement IC layout of innovative, high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 3nm, 5nm, 7nm and lower nodes following industry standard methodologies. Deliver layouts for Full Custom Memory group specializing in digital Memory circuits. IP layout will comprise of significant digital components. Adopting and putting in place the best layout practices/methodology for composing digital Memory layouts Follow company procedures and practices for IC layout activities. What we need to see: B. E/B Tech. / M Tech in Electronics or equivalent experience with 5+ Years of proven experience in Memory layout in advanced CMOS process. Detailed knowledge of industry standard EDA tools for Cadence. Experience with layout of high-performance memories of various types. Knowledge of Layout basics including the various types of bitcells, Decoder, LIO etc. (matching devices, symmetrical layout, signal shielding) Experience with floor planning, block level routing and macro level assembly. Detailed knowledge of top level verification including the EM/IR quality checks and detailed knowledge of layout dependent effects including LOD, Dummification, fills etc. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status #LI-Hybrid

NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life s work , to amplify human creativity and intelligence. As an NVIDIAN, you ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! We are looking for an Layout Design Engineer - someone who is excited to join a growing group of diverse individuals responsible for handling challenging high-speed digital and analog circuit designs. What youll be doing: Execute IC layout of cutting edge, high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 3nm, 5nm, 7nm and lower nodes following industry best practices. Deliver layouts for Circuit Solutions Group specializing in digital cum analog IPs. IP layout will comprise of significant digital components and some analog components. Adopting and putting in place best layout practices/methodology for composing Analog and digital layouts Follow company procedures and practices for IC layout activities. What we need to see: 2+ years of experience in high performance analog layout in advanced CMOS process. BE/M-Tech in Electrical & Electronics or equivalent experience. Thorough knowledge of industry standard EDA tools for Cadence. Experience with layout of high-performance analog blocks such as Current mirrors, Sense Amps, bandgaps etc. is required. Knowledge in analog design and layout guidelines, high speed IO, (matching devices, symmetrical layout, signal shielding, other analog specific guidelines) Experience with floor planning, block level routing and macro level assembly. Knowledge of high-performance analog layout techniques such as common centroid layout, matching, symmetrical layout, signal shielding, use of dummy devices, thermal aware layout with consideration for electro migration and other analog specific guidelines. Demonstrated experience with analog layout for silicon chips in mass production. Background with sub-micron design in foundry CMOS nodes 7nm finfet and below is preferred. Experience working in distributed design team is a plus. Requires self-starter with the ability to define and adhere to a schedule. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status. #LI-Hybrid

Develop and execute validation strategies for next-gen EDA tools. Create and test HDL designs (Verilog/VHDL) for tool validation. Automate testing workflows using Python, Tcl, or Bash scripting. Analyze and optimize digital design workflows for performance. Collaborate with cross-functional teams to troubleshoot and improve product reliability. What We re Looking For: B.Tech / M.Tech in Electronics or Electrical Engineering. 2-5 years of experience in digital design, EDA validation, or testing. Strong knowledge of Verilog, VHDL, and FPGA/ASIC design workflows. Proficiency in scripting languages (Python, Tcl, Bash). Familiarity with cloud-based EDA tools and validation methodologies.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. QCT is actively seeking candidates for VLSI Methodology and R&D positions. You will be part of the backend methodology team that develops innovative solutions for Qualcomms chip implementation flow. As a digital ASIC R&D Engineer, you will play a vital role in addressing challenges with Performance, Power, and Area (PPA) scaling tradeoffs to qualify technology entitlement of advance process nodes. You will be responsible for research and develop methods to improve efficiency of digital ASIC design flow and chip quality/yield. The job scope includes design automation, post-silicon debug and data mining. Required Skills Coding with Python, Perl, TCL and/or C++ Working knowledge in Digital VLSI implementation (netlist to GDS) STA Power Distribution Network (PDN) Hands on experience with EDA tools (Primetime, ICC2, Innovus, Tempus, etc.) Expected Experience: 2- 10 years of relevant industry experience Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

As a Scribe CAD Staff Engineer at Micron Technology, Inc., you will be enabling and deploying layout automation concepts to enhance memory design teams productivity. You will be collaborating with multiple global teams like CAD, Memory design, and Technology development teams. Responsibilities and Tasks include, but not limited to: Work closely with memory design and technology development teams and resolve their daily challenges and develop comprehensive solutions for future. Proactively identify problem areas for improvement, propose, and develop innovative solutions. Continuously evaluate and implement new tools and technologies to improve the current automation flows. Demonstrate growth mindset and work towards submitting patent disclosures and research papers. Provide guidance and mentorship to junior members of the team. Qualifications: Advanced understanding of PDK development/validation, EDA tools and CAD flows. Develop and enable programmatically defined P-cell (Parameterized layout generator) devices for memory layout modules. Implement advanced methodologies for layout automation which can be scalable between technologies and enhance design workflow. Good understanding of programming fundamentals, as well as exposure to various programming languages including: Skill/Skill++ (Cadence), Perl, Python, Tcl. Experience of developing physical verification collaterals using SVRF. Working experience of Physical Verification flow and analyzing/debugging DRC, ERC, LVS, DFM, Antenna and rule deck issues. Good understanding of basic CMOS process manufacturing and layout design rules. Working knowledge of Linux is a must. Excellent problem-solving skills with attention to detail. Ability to work in a dynamic environment. Proficiency in working effectively with global teams and stakeholders. 8+ years of relevant experience. Education: A Bachelors or Masters degree in Computer Science, Computer Engineering, Electrical Engineering or Electronics Engineering.

We are seeking a highly skilled Synthesis & Static Timing Analysis (STA) expert to join our Flows & Methodologies Team . This role requires strong analytical skills, attention to detail, and collaboration with cross-functional teams . Proficiency in EDA tools and digital design principles is essential. Location: Noida (Hybrid 3 days work in office) Experience: 6 to 15 years Key Responsibilities & Skills: Work with SoC cross-functional teams to define and develop Synthesis & STA methodologies for advanced nodes (3nm, 5nm, 16nm). Strong knowledge of RTL, Synthesis, LEC, VCLP, Timing Constraints, UPF, Timing Closure & Signoff . Experience with EDA tools such as Genus, Fusion Compiler, PrimeTime, Tempus, Conformal . Strong scripting skills in Perl, TCL, Python for automation and flow development. To apply, click on the Apply option or share your resume with Heena at heena.k@randstad.in

Designs, develops, and builds analog circuits in advanced process nodes for analog and mixedsignal IPs. Designs floorplans, performs circuit design, extracts chip parameters, and simulates analog behavior models. Creates test plans to verify design according to circuit and block microarchitecture specifications and evaluates test results. Verifies functionality to optimize circuit for power, performance, area, timing, and yield goals. Collaborates cross functionally to report design progress and collects, tracks, and resolves any performance and circuit design issues. Optimizes performance, power, area, and reduces leakage of circuits. Works with architecture and layout team to design circuit for best functionality, robustness, and electrical capabilities. Qualifications B.Tech / M.Tech/ Phd with with 3+ hands-on experience in high-speed analog circuit design, with a proven track record of successful projects. Expertise in designing and verifying analog circuits such as High-speed transmitter, recevier, amplifiers, PLLs, voltage regulators, and data converters. Proficiency in using EDA tools like Cadence Virtuoso, SPICE, or Synopsys.

We are seeking a highly skilled and experienced PDN (IR Drop & EM analysis) & PV (Physical Verification) expert to join our Flows & Methodologies Team . This role requires strong analytical skills, attention to detail, and collaboration with cross-functional teams. Proficiency in EDA tools and a solid understanding of digital design principles are essential for success. Location: Noida (Hybrid 3 days in office) Experience: 6 to 15 years Key Responsibilities & Skills: Work closely with SoC cross-functional teams to develop and define PDN & PV flow and methodologies for low geometry nodes (3nm, 5nm, 16nm). Hands-on experience in PDN (IR Drop & EM Analysis) and PV (Physical Verification) domains. Experience in PDN & PV signoff for advanced process nodes. Ability to debug PV issues (LVS, DRC, ERC, ANTENNA, ESD/LUP, etc.) and IR-EM-Power issues independently. Drive PDN & PV methodology and automation for enhanced design efficiency. To apply, click on the Apply option or share your resume at- heena.k@randstad.in

About The Role : Experience in Mixed-Signal layout design, holding bachelors degree To work independently on block levels analog layout design from schematic, estimating the Area, Optimizing Floorplan, Routing and Verifications. Firsthand experience in Critical Analog Layout design of blocks such as Temperature sensor, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc., Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence VLE/VXL, PVS, Assura and Calibre DRC/ LVS is a must. Understanding layout effects on the circuit such as speed, capacitance, power and area etc., Ability to understand design constraints and implement high-quality layouts. Multiple Tape out support experience will be an added advantage. Good people skills and critical thinking abilities to resolve the issue technically, and professionally. Excellent communication. Responsible for timely execution with high quality of layout design. Primary Skills Analog Layout Process or technology experience:TSMC 7nm, 5nm, 10nm,28nm, 45nm,40nm EDA Tools: Layout Editor:Cadence Virtuoso L, XL Physical verification:DRC,LVS,Calibre Secondary Skills IO layout

Staff Engineer Data Analytics (Design Enablement) Job Description : We are looking for a Staff Engineer for Data Analytics role as a part of the Design Enablement team. The responsibilities include working closely with SoC cross-functional teams to develop and define methodologies for data analytics to meet SoC & IP level objectives. Specific skills & knowledge : A degree in Electronics Engineering or a related field 6-10 years of experience in Data Analytics Proficiency in relevant EDA tools like Synopsys, Cadence, and Mentor Graphics and a solid understanding of digital design principles Strong scripting skills for automation and flow development using PERL/TCL/Python GIT : Proficiency in using GIT & experience with GIT repositories such as GitHub, GitLab or Bitbucket Python : Strong knowledge of Python programming & Familiarity with Python libraries & tools for development, testing & debugging Experience in writing clean, efficient & maintainable code Understanding of Python’s standard library & its applications in various domains Web Development : Proficiency in front-end technologies such as HTML, CSS & JavaScript Experience with front-end frameworks like React, Angular or Vue.js Understanding of web development best practices, including responsive design, cross-browser compatibility & performance optimization Excellent communication skills, problem-solving abilities, and attention to detail

Develop and maintain OPC code (recipe) for various technodes Develop and maintain ORC code (recipe) for various technodes Work on different aspects of OPC code - like SRAFs, MRC, Booleans Do ORC review with required details and complete within agreed time Develop and maintain OPC code (recipe) for various technodes (like 12/14nm) supporting world wide fabs Develop and maintain ORC code (recipe) for various technodes (like 12/14>) supporting world wide fabs Work on different aspects of OPC code - like SRAFs, MRC, Booleans Do ORC review with required details and complete within agreed time Ability to work in a dynamic collaborative environment which requires strong teaming skills with Engineers, Technicians, Managers, and IT Interact with other GF Teams such as Fab Litho, Frame and Fab Integration Engineers to provide feedback to Release for D2M Reviews Disposition Ability to solve complex technical problems and contribute to multiple projects at the same time Strong ability to learn and explore new technologies, opportunities, and continuous improvement Familiarity with Fab processing is preferred Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety Security requirements and programs Required Qualifications: MS/MTech +internship is preferred Specialization on Microelectronics/VLSI or related fields Fluency in English Language - written verbal Basic coding familiarity Exposure to Mentor graphics EDA tools and/or SVRF language Familiarity with perl or tcl or python or shell is a plus. Familiarity with OPC is a big plus