160 Eda Tools Jobs - Page 3

Number of Open Positions: 7 Experience: 4 to 7+ years Location: Bangalore : We are seeking highly skilled and motivated DFT-DV Engineers to join our dynamic team in Bangalore. As a DFT-DV Engineer, you will play a pivotal role in ensuring the quality and reliability of our digital designs through Design for Test (DFT) and Design Verification (DV) methodologies. The ideal candidates should possess a minimum of 4 to 7+ years of experience in the field, with a strong background in DFT DV flow, JTAG, MBIST, SCAN, PG, PHY-LP, and BSCAN. Key Responsibilities: DFT Implementation: Collaborate with design and verification teams to define and implement DFT strategies and methodologies that enable efficient testing of complex digital designs. Scan and ATPG: Develop and maintain scan insertion, Automatic Test Pattern Generation (ATPG), and compression methodologies to achieve high test coverage. Memory BIST: Implement and verify Memory Built-In Self-Test (MBIST) solutions for embedded memories in the design. JTAG and Boundary Scan: Develop JTAG and Boundary Scan solutions to facilitate efficient testing and debugging of digital designs. Power Management: Work on Power Gating (PG) techniques to optimize power consumption during testing. PHY-LP Integration: Collaborate with PHY teams to ensure seamless integration of low-power features into the design. BSCAN Integration: Implement Boundary Scan (BSCAN) infrastructure to enhance testability and debug capabilities. Verification: Verify DFT features and ensure their correctness through simulation and formal verification. Documentation: Prepare detailed documentation, including DFT specifications, test plans, and reports. Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or related field. 4 to 7+ years of experience in DFT-DV engineering. Strong expertise in DFT methodologies, including scan, ATPG, MBIST, JTAG, BSCAN, and PG. Proficiency in industry-standard EDA tools for DFT implementation. Experience with low-power design and PHY-LP integration is a plus. Excellent problem-solving skills and attention to detail. Strong communication and teamwork skills. If you are a proactive and results-oriented engineer with a passion for ensuring the quality and reliability of digital designs, we encourage you to apply. Join us in our mission to develop cutting-edge technology and make a significant impact in the semiconductor industry. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Calling all innovators and creators!Were hiring RTL Design Engineers for Bangalore to work on complex ASICdesigns and integrations.Experience Required3"“25 YearsKey Skills: RTL design, low-power methodologies, scripting (Perl, Python, TCL)Join us and design the future of technology! Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Strong understanding of DFX concepts: DFT, DFM, DFA, DFR Experience in semiconductor, electronic hardware, or embedded product development Proficiency in DFT/DFM tools and methodologies FMEA, FTA, reliability analysis, and root cause problem solving

As an Analog Layout Engineer at ARF Design Pvt Ltd, you will be responsible for designing and developing analog layout IP blocks and full-chip integration. Your role will involve performing and resolving LVS/DRC violations independently, collaborating with circuit design teams to optimize layout quality and performance, and ensuring layouts meet design matching and parasitic constraints. You will have the opportunity to work with advanced nodes like 7nm, 16nm, and 28nm, leveraging your 3+ years of relevant Analog Layout experience. Key Responsibilities: - Design and develop analog layout IP blocks and full-chip integration - Perform and resolve LVS/DRC violations independently - Collaborate with circuit design teams to optimize layout quality and performance - Ensure layouts meet design matching and parasitic constraints - Work with advanced nodes like 7nm, 16nm, and 28nm Required Skills: - 3+ yrs of relevant Analog Layout experience - Proficiency in LVS/DRC checks and EDA tools - Experience with lower technology nodes (3nm, 5nm, 7nm, 10nm, 16nm / 28nm ETC) - Good understanding of layout matching, parasitic extraction, and floor planning - Strong verbal and written communication skills - Ability to work independently and within cross-functional teams In this role, you will be a Circuit Design Engineer at ARF Design, where you will be working on the design of building blocks used in high-speed IPs such as DDR/LPDDR/HBM/UCIe/MIPI/PCIe. Your responsibilities will include deriving circuit block level specifications from top-level specifications, performing optimized transistor-level design of analog and custom digital blocks, running SPICE simulations to meet detailed specifications, and guiding layout design for best performance, matching, and power delivery. Key Responsibilities: - Derive circuit block level specifications from top-level specifications - Perform optimized transistor-level design of analog and custom digital blocks - Run SPICE simulations to meet detailed specifications - Guide layout design for best performance, matching, and power delivery - Characterize design performance across PVT + mismatch corners and reliability checks (aging, EM, IR) - Generate and deliver behavioral (Verilog), timing (LIB), and physical (LEF) models of circuits - Conduct design reviews at various phases/maturity of the design Qualifications: - BE/M-Tech in Electrical & Electronics - Strong fundamentals in RLC circuits, CMOS devices, and digital design concepts (e.g., counters, FSMs) - Experience with custom design environments (e.g., Cadence Virtuoso, Synopsys Custom Design Family) and SPICE simulators - Collaborative mindset with a positive attitude If you have 3+ years of experience and are interested in these exciting opportunities, please share your updated resume [Name_Post_Exp] to divyas@arf-desgn.com. Join ARF Design for a chance to work on advanced nodes with fast-track interview and onboarding processes.,

As a Systems Engineer at Texas Instruments (TI), you will have the opportunity to work in a vibrant and dynamic team-oriented environment, contributing to a variety of state-of-the-art applications daily. Your responsibilities will include researching and defining new product strategies, analyzing key end-equipment in various sectors, negotiating IC development tradeoffs, and serving as the technical expert for product ramp-up. You will also be involved in silicon system evaluation, application support, troubleshooting customer issues, and driving design wins for new and existing products. In this role, you will collaborate closely with design, product, test, packaging, marketing, and sales teams to bring quick resolutions to customer problems and assist in revenue planning for the organization. Additionally, you will be responsible for creating technical literature, supporting central applications engineering and sales organizations, and contributing to the revenue growth through the adoption of new products. To qualify for this position, you should have a Bachelor's degree in Electrical Engineering, a minimum of 5 years of relevant experience, and a strong understanding of analog/mixed-signal IC's and their applications. Strong customer-facing skills, familiarity with lab equipment, and system-level circuit modeling expertise with EDA tools, SPICE, and Matlab are essential. Preferred qualifications include the ability to establish strong relationships with key stakeholders, excellent communication skills, strong problem-solving abilities, and effective collaboration skills across different functions. At TI, we empower our employees to own their career and development, collaborating with some of the brightest minds to shape the future of electronics. We value diversity, innovation, and inclusivity, and we are committed to creating a better world through affordable semiconductor technology. If you are passionate about electronics and want to be part of a team that drives innovation forward, we welcome your application. Texas Instruments Incorporated is a global semiconductor company that designs, manufactures, and sells analog and embedded processing chips for various markets. We are dedicated to creating a better world through affordable electronics, building upon generations of innovation to make technology more reliable, affordable, and energy-efficient. Learn more about us at TI.com. Texas Instruments is an equal opportunity employer that supports a diverse and inclusive work environment. If you are interested in joining our team, please apply to this requisition.,

As a member of the Common Hardware Group (CHG) at Cisco, you will be part of a team that delivers cutting-edge silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. Our work involves designing networking hardware for Enterprises, Service Providers, Public Sector, and Non-Profit Organizations worldwide. Join us in shaping Cisco's groundbreaking solutions by participating in the design, development, and testing of advanced ASICs that are at the forefront of the industry. Your role will involve implementing Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug, and diagnostics requirements of the designs. You will collaborate with multi-functional teams to develop innovative DFT IP and play a crucial role in integrating testability features in the RTL. Working closely with design and PD teams, you will ensure the seamless integration and validation of test logic throughout all phases of implementation and post-silicon validation flows. Your team will contribute to the creation of innovative Hardware DFT and physical design aspects for new silicon device models, bare die, and stacked die. You will drive re-usable test and debug strategies while showcasing your ability to craft solutions and debug with minimal mentorship. To excel in this role, you are required to have a Bachelor's or Master's Degree in Electrical or Computer Engineering along with a minimum of 10 years of relevant experience. Your expertise should encompass knowledge of the latest trends in DFT, test, and silicon engineering. Proficiency in Jtag protocols, Scan and BIST architectures, ATPG, EDA tools, and verification skills like System Verilog Logic Equivalency checking will be essential. Preferred qualifications include experience in Verilog design, DFT CAD development, Test Static Timing Analysis, and Post-silicon validation using DFT patterns. Your background in developing custom DFT logic and IP integration, familiarity with functional verification, and scripting skills like Tcl, Python, or Perl will be advantageous. At Cisco, we value diversity, innovation, and collaboration. We empower our employees to bring their unique talents to work, driving positive change and powering an inclusive future for all. As a company that embraces digital transformation, we encourage creativity, innovation, and a culture that supports learning and growth. Join us at Cisco, where every individual is valued for their contributions, and together, we make a difference in the world of technology and networking.,

The company is seeking an individual with expertise in underwriting technology infrastructure projects, specifically in the semiconductor domain. You will be responsible for assisting the leadership team in completing the final investment due diligence process for a $500M cross-border semiconductor manufacturing project in India and the USA. Your main responsibilities will include reviewing and responding to due diligence questionnaires from global investors and fund managers, providing a detailed underwriting analysis of the semiconductor project, and supporting documentation related to financial modeling, technology validation, operational planning, risk identification, and compliance with relevant standards. You will also act as a technical-underwriting contact in discussions with investors and ensure compliance with US SEC, UK FCA, and RBI norms. The ideal candidate should have at least 10 years of experience in underwriting large-scale technology or semiconductor projects, exposure to due diligence reviews for venture capital, PE, or sovereign fund investments, a strong technical understanding of semiconductor manufacturing, and experience working with leading chip firms. Familiarity with cross-jurisdictional financial structuring is also required. The engagement duration for this role is from July 15 to August 31, 2025, with a possibility of extension for advisory support during fund disbursal or board review. To apply or refer someone for this role, please send your resume or reference to devdutta@msn.com with the subject line: Semiconductor Project Underwriter Due Diligence Role.,

The successful candidate will operate as a senior member of the CAD department library team. Responsibilities include creating and updating component CAD schematic symbols and footprint geometry. You will interface with internal staff, PWB designers, department managers, component engineers, CAD tool administrators, and outside subcontractors in the fast-paced execution of a variety of circuit board projects. There is growth potential for a permanent position with managerial responsibility. Preferred Qualifications: - Bachelor's or Associate degree in Electrical/Electronics, Computer Science, Mathematics, or a related field. - 4+ years of experience in CAD library and/or PWB design. - Working knowledge in the use of EDA tools, preferably Siemens/Mentor Xpedition and/or Cadence Allegro. - Working knowledge of Agile or other PLM tools. - Working knowledge of AutoCAD/3D tools. - Basic understanding of Design for Manufacturing/Assembly (DFM/DFA) and utilizing this understanding to create CAD library parts. - Basic understanding and interpretation of datasheets and engineering drawings. - Ability to work effectively with internal and external teams. Principal Duties and Responsibilities: - Analyze component specifications and determine the best way to create CAD libraries that meet customer requirements. - Develop CAD library symbols/parts from datasheets and specifications, often with input from team members. - Stay informed about new/emerging technologies, especially as packages become smaller with higher pin count and finer pitch. - Have a basic understanding/working knowledge of MS Office tools. - Collaborate cross-functionally to expedite issues and provide solutions. - Look for opportunities for process improvements with guidance from others. Level of Responsibility: - Work under close supervision. - Responsible for your work with limited decision-making. Impact of decisions is readily apparent. - Require verbal and written communication skills to convey basic, routine factual information about day-to-day activities to knowledgeable individuals. - Most tasks require multiple steps that can be performed in various orders; planning and prioritization are necessary for effective task completion. - Some creativity may be needed to troubleshoot technical problems or deal with novel circumstances. - Deductive problem-solving is required to solve moderately complex problems; most problems have defined processes of diagnosis/detection; some limited data analysis may be needed.,

: 6 to 8 years of Semiconductor industry experience in Custom Mixed-Signal layout design with a bachelors degree in electrical/Electronic Engineering. Able to deliver Custom analog layouts independently from schematic to layout generation, estimating the area, optimizing floorplan, routing, and complete verification flows. Firsthand experience in critical analog layout design blocks such as Temperature sensor, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc. Good at LVS/DRC debugging skills and other verifications for lower technology nodes - 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence VLE/VXL, PVS, Assura and Calibre DRC/ LVS is necessary. Understanding layout effects on the circuit such as speed, capacitance, power, and area etc. Ability to understand design constraints and implement high-quality layouts. Multiple Tape out support experience and collaborating with cross functional teams will be an added advantage. Good people skills and critical thinking abilities to resolve the issue technically and professionally. Excellent communication. Responsible for timely execution with high quality of layout design. Multiple foundries experience is an added plus. Minimum Educational Qualification : Educational Bachelor"s, Electrical or Electronics Engineering or equivalent Role And Responsibilities Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support. Perform layout verification like LVS/DRC/Antenna, EM, quality check and documentation. Responsible for on-time delivery of block-level/top-level layouts with acceptable quality. Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment. Guide junior team-members in their execution of Sub block-level layouts & review their work Should have good experience in working with cross-functional team. Ensure standard processes and procedures are followed to resolve all client queries. Handle technical escalations through effective diagnosis and troubleshooting of client queries Manage and resolve technical roadblocks/ escalations to timely deliverable with high quality. Troubleshoot all client queries in a user-friendly, courteous, and professional manner. Offer alternative solutions to clients (where appropriate) with the objective of retaining customers" and clients" business. Build people capability to ensure operational excellence and maintain superior customer service levels of the existing account/client. Contribute to effective project-management. Effectively communicating with engineering teams in different Geographical locations to assure the success of the layout project. Works in the area of Software Engineering, which encompasses the development, maintenance and optimization of software solutions/applications.1. Applies scientific methods to analyse and solve software engineering problems.2. He/she is responsible for the development and application of software engineering practice and knowledge, in research, design, development and maintenance.3. His/her work requires the exercise of original thought and judgement and the ability to supervise the technical and administrative work of other software engineers.4. The software engineer builds skills and expertise of his/her software engineering discipline to reach standard software engineer skills expectations for the applicable role, as defined in Professional Communities.5. The software engineer collaborates and acts as team player with other software engineers and stakeholders.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Exciting opportunity to work on Digital Flows/Methodologies architecture and development in energetic multi-site CAD team at Qualcomm.Our team support Simulation, Emulation, Formal Verification and Post Silicon domains providing ample opportunities to grow and contribute. Responsibilities As a Design Automation Engineer, you will work with RTL, architecture, design, DV, software, and silicon verification users. Develops, maintains, debugs and tests CPU Design Methodologies using Commercial EDA tools Defines and creates flows/scripts to help design teams execute Front-End (RTL) flows seamlessly Create unit, integration, regression, and/or system-level tests to thoroughly validate new features or changes. Work closely with Eng IT teams to setup flows which work well with the Engineering Compute Infra at multiple Datacenters Work closely with design teams to define methodologies, drive flow development, and deploy vendor tools Interfaces with external vendors to define, drive and incorporate the latest design solutions to improve productivity and time to market. Support design engineers on the flow setup and resolve their queries, automate tasks through appropriate tools and scripting. Review and debug code to identify and fix code problems. Qualifications Proficient with Python development and strong working knowledge of Linux operating systems Must have worked on Digital flows/methodologies development in the DV domains. Should have proficient skills with one of DV related tools Xcelium/VCS/vManager/Indago/Verdi or equivalent. Experience with CI/CD platform (like Airflow and Jenkins) and Version Control System (like Perforce and/or Git). MS/BS in Electrical/Computer Engineering with 8-14 years of demonstrated experience in CAD or EDA tools flows architecture, development, and support. Demonstrated experience with various EDA software, flows, and architectures & driving EDA vendors to provide feature enhancements and bugfixes. Ability to document design methodologies & provide training on tools and workflows to design teams Strong skills in debugging and analyzing techniques to understand existing scripts/flows; Ability to work independently and explore new domains Proven track record of pushing Prior experience debugging vendor tool problems Strong written and verbal interpersonal skills and track record of success in a collaborative team environment Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As SoC Verification engineer, the candidate will be responsible to own SoC Interconnect DV (Connectivity matrix, Coherency, Clock gating, Performance etc) during the project work. Responsibilities Understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design. Work alongside other members of the verification team to analyze, develop and execute verification test cases and able to provide relevant solution to issue. Collaborate with architects, designers, and pre and post silicon verification teams. Skillsets/Requirements B.E/B.Tech/M.E/M.Tech in Electronics with 7+ year experience in verification domain. Good understanding of Soc level verification testbench and flows. Prior work on NoC/Interconnects end to end verification with solid understanding on to Bus protocols, Coherency, Performance, Latency, clock gating etc. Working knowledge of Interconnect architecture and Bus protocols like AMBA - ACE/CHI/AXI. Solid hands-on working experience on System Verilog and UVM methodology. Expert in handling protocol BFM/VIP integration and traffic sequence development. Experience in coding assertions and functional coverage bins. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Exp : 3- 5 Yrs Position : Senior or Lead Expertise : Power fundamentals Good knowledge of PTPX Good knowledge of CLP Knowledge of design verification, RTL coding, synthesis, and physical design Protocol knowledge of , DDR, CHI, Cache, computer organization, bus protocol, Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

As a digital chip designer and customer support specialist, you will collaborate closely with customers to understand their design requirements and provide technical support throughout the implementation phase. Your responsibilities will include identifying, troubleshooting, and resolving design issues such as DRC, LVS, and other verification checks to ensure successful tapeout. You will be hands-on in utilizing relevant EDA tools like Innovus, IC compiler, Calibre, PrimeTime, etc. Additionally, you will assist in the tapeout process, ensuring that all design files are correctly prepared and submitted for manufacturing. To excel in this role, you must hold a Bachelor's or Master's degree in Electrical Engineering or a related field. A minimum of 8 years of proven experience as a digital chip designer and customer support professional is required. Strong problem-solving skills and the ability to work effectively under pressure are crucial attributes for success in this position. Excellent communication and interpersonal skills will be essential in engaging with customers and collaborating effectively. Proficiency in EDA tools such as Cadence, Synopsys, and Mentor Graphics is a must to meet the demands of this role.,

About Tata Electronics: Tata Electronics, a wholly owned subsidiary of Tata Sons Pvt. Ltd., is pioneering the development of India's first AI-enabled state-of-the-art Semiconductor Foundry. The cutting-edge facility is dedicated to manufacturing chips for a wide range of applications including power management IC, display drivers, microcontrollers (MCU), and high-performance computing logic. These chips cater to the increasing demand in sectors like automotive, computing, data storage, wireless communications, and artificial intelligence. Tata Electronics, as part of the Tata group, operates globally in over 100 countries across six continents. With a core mission of enhancing the quality of life in communities worldwide, the Tata Group focuses on long-term stakeholder value creation through trustworthy leadership. Key Responsibilities: - Collaborate closely with customers to comprehend their design needs and offer technical assistance throughout the project lifecycle. - Identify, troubleshoot, and resolve design challenges such as DRC, LVS, and other verification checks to ensure seamless tapeout. - Utilize expertise in layout design and employ layout techniques to enhance performance. - Support the tapeout process by ensuring accurate preparation and submission of all design files for manufacturing. - Proficient in utilizing EDA tools like Virtuoso, Custom compiler, Calibre, PrimeTime, and others. - Willingness to travel to customer sites on an ad hoc basis. Qualifications: - Bachelor's or master's degree in electrical engineering or a related field. - Demonstrated track record of at least 8 years as an analog chip designer/customer support specialist. - Strong problem-solving abilities and capability to perform effectively under pressure. - Excellent communication and interpersonal skills. - Hands-on experience with EDA tools such as Cadence, Synopsys, and Mentor Graphics. - Knowledge of Tapeout processes and GDS file preparation.,

As a Digital DV Engineer at our company, you will be responsible for developing and maintaining reusable, scalable, and modular processor-level verification environments using UVM System Verilog. Your role will involve designing and implementing test plans, testbenches, and directed/random tests to validate ARM M-series and RISC-V processor designs, with exposure to DSP processors considered a plus. You will integrate and verify processor subsystems in SoC environments, ensuring seamless interaction with other components. Your tasks will also include executing regression tests across various scenarios and corner cases to ensure functionality and robustness. You will be expected to analyze simulation results, debug issues, and provide detailed reports to design and verification teams. Collaboration with cross-functional teams, including architecture, software, and hardware, will be essential to define verification strategies and ensure alignment. Additionally, you will optimize verification flows, improve coverage metrics, and manage verification closure for processors. To be successful in this role, you should possess a Bachelor's or Master's degree in Electrical/Electronic Engineering or a related field, along with at least 5 years of hands-on experience in processor verification. Proficiency in UVM SystemVerilog, a solid understanding of processor architectures, instruction sets, and pipeline designs, as well as knowledge of AMBA protocols and interfaces used in SoCs are required. Strong experience with C programming for processor-level test development and familiarity with verification methodologies such as constrained random testing, coverage-driven verification, and assertion-based verification are essential. Proficiency in using EDA tools for simulation, debugging, and coverage analysis is also expected, along with the ability to debug RTL-level issues and collaborate closely with design engineers for issue resolution. This is a full-time position located in Bangalore, requiring a minimum of 7 years of experience in the field. The ideal candidate should be available to start within 0-30 days of notice period.,

The Sales Engineer is a customer facing role, responsible for the complete sales process - demand creation, mapping of accounts and closure. The candidate should be able to effectively communicate EDA / MCAD product capabilities and the benefits of the solutions through presentations and sales demonstrations. Conduct discovery and requirements gathering sessions to analyze and understand customer needs, workflows and technical requirements. Develop and/or collate sample documents, applications and other sales enablement materials for use during the sales and marketing sessions. Collaborate with Technical and services teams to specify, recommend and architect comprehensive customer solutions Required Skills: • Sales experience in Aerospace & Defense industry • Knowledge on EDA tools Siemens EDA / Cadence / Synopsys • Knowledge on MCAD tools – Cero(ProE)/UGNX/Catia/Solid edge/Solid works/Inventor • Knowledge on CAE Tools – Ansys/Nastran/Adams/Altair • Must be aware about the complete sales cycle • He should have handled defense accounts in South preferably. Responsibilities: • Discussing customer's needs and identifying suitable product mix • Conducting presentation on products/concepts • Handling sales queries and problems of clients • Conducting product seminars and conferences at industry Soft Skills: • Excellence in teamwork. • Possess conceptual, analytical and presentation skills. • Creative, dynamic & confident. • Should be an initiator Able to work under pressure. • Should be able to work under different cultures. • Willingness to travel. • Good convincing skills are required Travel: Expected Travel 7075%

Designation - Sales Engineer Location - Pune/Bangalore/Kolkata/Delhi/Hyderabad Job Summery: The Sales Engineer is a customer facing role, responsible for the complete sales process - demand creation, mapping of accounts and closure. The candidate should be able to effectively communicate EDA / MCAD product capabilities and the benefits of the solutions through presentations and sales demonstrations. Conduct discovery and requirements gathering sessions to analyze and understand customer needs, workflows and technical requirements. Develop and/or collate sample documents, applications and other sales enablement materials for use during the sales and marketing sessions. Collaborate with Technical and services teams to specify, recommend and architect comprehensive customer solutions Required Skills : Sales experience in Aerospace & Defense industry Knowledge on EDA tools Siemens EDA / Cadence / Synopsys Knowledge on MCAD tools Cero(ProE)/UGNX/Catia/Solid edge/Solid works/Inventor Knowledge on CAE Tools Ansys/Nastran/Adams/Altair Must be aware about the complete sales cycle He should have handled defense accounts in South preferably. Interested candidates kindly share your resume on nishas@smart-source.in Regards, Nisha Singh Smart Source

Job Description: We are looking for experienced DV Lead Engineers with a strong background in SystemVerilog, UVM, and protocol-based SoC/IP verification . The ideal candidate will have excellent debugging and leadership skills, with hands-on experience in building testbenches and leading verification teams. Key Responsibilities: Build comprehensive test plans , test cases , and functional coverage from specification documents Architect and develop UVM-based testbenches and verification environments Work with high-speed protocols such as AXI, AHB, APB, PCIe Hands-on debugging and simulation using Synopsys and Cadence tools Mentor junior team members, collaborate cross-functionally, and lead project execution Good to Have: Scripting and automation (Perl/Python/TCL) Experience with UPF simulations , GLS , and Formal Verification Exposure to SoC-level verification Strong communication and leadership abilities

Position: - Sales Engineer / Sr Sales Engineer- ESG Qualification: BE/ B Tech. in Electronics / Mechanical Experience: 2- 5 Years Location: Delhi /Hyderabad /Pune/ Kolkata The Sales Engineer is a customer facing role, responsible for the complete sales process - demand creation, mapping of accounts and closure. The candidate should be able to effectively communicate EDA / MCAD product capabilities and the benefits of the solutions through presentations and sales demonstrations. Conduct discovery and requirements gathering sessions to analyze and understand customer needs, workflows and technical requirements. Develop and/or collate sample documents, applications and other sales enablement materials for use during the sales and marketing sessions. Collaborate with Technical and services teams to specify, recommend and architect comprehensive customer solutions Required Skills : Relevant Sales experience in Defense / Institutional Sales /Private Commercial Sales/Academics Sales experience in Application or Engineering Software Knowledge on EDA tools Siemens EDA / Cadence / Synopsys Knowledge on MCAD tools Cero (ProE)/UGNX/Catia/Solid edge/Solid works/Inventor Knowledge on CAE Tools – Ansys/Nastran/Adams/Altair Knowledge of Procurement procedures such as Tender, Gem portal, E-tender, etc. Must be aware about the complete sales cycle Responsibilities: Identify customer needs and recommend suitable products/solutions Deliver product/concept presentations and conduct industry seminars Resolve client queries and manage sales concerns Capable of analyzing the merit of opportunities Skilled in identifying customer pain points Soft Skills: Team-oriented with strong analytical and presentation skills Creative, confident, and proactive Able to perform under pressure and meet targets Culturally adaptable with strong convincing skills Willing to travel extensively (70–75%) Role & responsibilities Preferred candidate profile

You will collaborate with customers to understand their design requirements and provide technical support throughout the implementation phase. Your responsibilities will include identifying, troubleshooting, and resolving design issues such as DRC, LVS, and other verification checks to ensure successful tapeout. It is essential for you to be hands-on in relevant EDA tools like Innovus, IC compiler, Calibre, PrimeTime etc. Additionally, you will assist in the tapeout process, ensuring all design files are correctly prepared and submitted for manufacturing. To qualify for this role, you should hold a Bachelor's or Master's degree in Electrical Engineering or a related field. You must have proven experience of at least 8 years as a digital chip designer and in customer support. Strong problem-solving skills and the ability to work under pressure are crucial for this position. Excellent communication and interpersonal skills will be necessary to effectively collaborate with team members and customers. Hands-on experience with EDA tools such as Cadence, Synopsys, and Mentor Graphics is also required for this role.,

Job Description Position: - Regional Manager - ESG (Govt/ defense/enterprise Sales) Qualification: BE/ B Tech/M Tech. in Electronics or Mechanical Experience: 10-12 years. Location: Pune / Hyderabad Annual CTC: - As per Industry Standard Job Summary: We are seeking a highly motivated and experienced Regional Sales Manager to lead business development and sales efforts for our EDA/CAE software solutions in the Academic, Government and defense sector . The ideal candidate will have a strong technical understanding of engineering simulation/design tools, a proven track record in enterprise sales, and experience working with government agencies, defence labs, and public sector clients. He will be responsible for executing the regions business plans along with the team reporting to him and will be in customer-facing role, responsible for the complete sales process - demand creation, mapping of accounts and closure. He Should have deep understanding of decision process and procurement process of various segments like PSU/ Defense/ Research organizations/Academic institutes. Key Responsibilities: Must Monitor and Mentor the regional sales team and drive sales and business development of EDA/CAE solutions within the assigned region. Identify, qualify, and close opportunities with defense agencies, research labs, and public sector entities. Build and maintain strong relationships with key stakeholders, including procurement officers, engineers, and technical decision-makers. Collaborate with application engineers and product specialists to deliver technical presentations, proofs of concept, and demonstrations. Develop and execute regional sales plans aligned with corporate objectives and revenue targets. Monitor government tenders, RFPs, and RFQs; coordinate proposal responses with internal teams. Stay updated on government procurement regulations and compliance requirements. Represent the company at industry conferences, defense expos, and government networking events. Role & responsibilities Preferred candidate profile Knowledge of tools like MATLAB/Simulink, Ansys, Altair tools, Medini Analyze, Relyence, or reliability and safety analysis tools. Good technical knowledge Excellent team management skills Possess conceptual, analytical and strong communication and presentation skills. Ability to make quick decisions and fast action. Understanding of business tactics and agility Good understanding of Sales cycle, partner ecosystem and relationship management.

Job Requirements Masters degree in Electrical Engineering or a related field Experience with industry-standard physical design tools (Cadence, Synopsys, Mentor Graphics) Knowledge of advanced process nodes (7nm, 5nm, etc. ) Experience with scripting languages such as Python, TCL, or Perl Strong understanding of VLSI design principles Experience in low-power design techniques Bachelors or Masters degree in Electrical Engineering or related field Expert knowledge of industry-standard EDA tools for physical design and verification, such as Synopsys ICC, Primetime, and StarRC Proven experience with advanced physical implementation techniques, such as multi-patterning, layout-dependent effects, and low-power design Excellent analytical and problem-solving skills Strong interpersonal and communication skills with the ability to collaborate effectively with cross-functional teams Self-motivated and able to work independently in a fast-paced and dynamic environment Work Experience Masters degree in Electrical Engineering or a related field Experience with industry-standard physical design tools (Cadence, Synopsys, Mentor Graphics) Knowledge of advanced process nodes (7nm, 5nm, etc. ) Experience with scripting languages such as Python, TCL, or Perl Strong understanding of VLSI design principles Experience in low-power design techniques Bachelors or Masters degree in Electrical Engineering or related field Expert knowledge of industry-standard EDA tools for physical design and verification, such as Synopsys ICC, Primetime, and StarRC Proven experience with advanced physical implementation techniques, such as multi-patterning, layout-dependent effects, and low-power design Excellent analytical and problem-solving skills

Experience or strong interest in developing memory compilers, addressing layout-related issues, and ensuring optimization. Excellent problem-solving skills in Routing Congestion, Physical Verification in Custom Layout. Sound knowledge and experience for verification checks like DRC / LVS / ERC / Antenna / LPE / DFM etc. Knowledge of various analog layout techniques, understanding of various circuit principles as affected by Layouts such as speed, capacitance, power, noise, and area. Excellent hands-on experience in industry standard layout and verification tools in a Linux environment of Cadence and Mentor EDA tools. Power user of VirtuosoXL. Excellent Leadership skills and Mentor & guide team members in execution of Layout and review their work outputs for quality and deliveryExcellent communication skills and proactive at work. Excellent communication skills and proactive at work

About Us: Silcosys Solutions Private Limited is a pioneer in semiconductor innovation, committed to delivering cutting-edge analog design solutions that power the future of technology. If you are eager to work on impactful projects and advance your expertise, we invite you to join our dynamic team. Job Description: As an RTL Design Engineer, you will be responsible for designing and implementing high-quality RTL code for complex digital blocks and subsystems. You will collaborate with architects, verification, and physical design teams to create designs that meet functional, performance, and power requirements. Responsibilities: Develop RTL designs for digital IPs, subsystems, and SoCs based on architectural specifications. Collaborate with architects and system engineers to translate high-level requirements into detailed micro-architecture. Perform design optimizations for area, power, and performance. Conduct design reviews and ensure compliance with coding standards and best practices. Work closely with verification teams to develop test plans and ensure 100% functional coverage. Debug and resolve design and integration issues during simulation and post-silicon validation. Participate in timing analysis and closure in collaboration with the physical design team. Document design specifications, test cases, and user guides for IP and SoC designs. Requirements: Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field. 2-10 years of experience in RTL design and implementation for VLSI systems. Strong expertise in Verilog, SystemVerilog, and RTL design methodologies. Solid understanding of digital design concepts such as pipelining, clock domain crossing, and low-power design techniques. Experience with EDA tools like Synopsys Design Compiler, Cadence Genus, or equivalent. Proficiency in scripting languages (Python, Perl, TCL) for design automation. Familiarity with SoC interfaces and protocols like AXI, AHB, PCIe, USB, or DDR. Experience in static timing analysis (STA) and timing closure workflows. Strong problem-solving skills and the ability to debug complex design issues. Excellent communication and collaboration skills to work effectively in a team environment. Preferred Qualifications: Experience with low-power design and multi-clock domain systems. Knowledge of advanced process nodes (e.g., 7nm, 5nm, or below) and FinFET technologies. Exposure to formal verification methodologies. Experience in hardware-software co-design and FPGA prototyping. Familiarity with machine learning or AI-based RTL optimizations. Why Join Us Work on groundbreaking projects in VLSI design and technology. Collaborate with a team of industry experts in a supportive and innovative environment. Opportunities for career growth and continuous learning. Competitive salary and benefits. How to Apply: If this role excites you, submit your updated resume at info@silcosys.com and any relevant project portfolios today. Join Silcosys Solutions Private Limited and shape the future of analog design!,

Experience in handling STA of multi-power domain designs & constraint mode merging. Job Description In your new role you will: Defining and verification of STA constraint for Functional and Test/SCANModes. Defining PVT s corners required for covering all desired scenarios for a design Knowledge on OCV/AOCV/POCV derates. Understanding of Prime-Time and TEMPUS tools, which helps in quick debugging of design/timing issues. VASTA timing closure based on chip IR drop. Knowledge on signal SI analysis and PT-PX flow. Your Profile You are best equipped for this task if you have: BE/B.Tech/M.Tech with 8+ years. Project leading knowledge is preferred. Delivery oriented, Passionate to learn and explore, Transparent in communication, Flexibility related to project situations. Candidate should have strong STA fundamentals. Has done timing sign-off including timing margin calculations. Independently, hands-on STA lead of projects. Experience in handling STA of multi-power domain designs & constraint mode merging. STA flow development , abstraction with bottleneck identification. Proficient in design margins and SDC constructs. TAT reduction inmulti-mode, multi power domain/designs. Generate timing ECOs for Physical design. Drive ambitious schedules and enables dependent teams to accomplish. Interface to design team and PD team and drive TAT reduction for PD. Has experience in mentoring junior engineers. Proficient with EDA tools from Synopsys/Cadence . Excellent analytical & communication skills. Shown ability to collaborate in a multi-functional environment, cross-site or cross-time zone. Proficient in Tcl and Perl or other scripting relevant language is a plus. Contact: swati.gupta@infineon.com We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant s experience and skills. Learn more about our various contact channels. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon.