160 Eda Tools Jobs - Page 2

As an Analog Layout Engineer at ARF Design Pvt Ltd, you will be responsible for designing and developing analog layout IP blocks and integrating them into full-chip designs. Your expertise in lower technology nodes, physical layout techniques, and verification processes will be crucial for success in this role. You will collaborate with circuit design teams to optimize layout quality and performance, ensuring that layouts meet design matching and parasitic constraints. Working with advanced nodes like 7nm, 16nm, and 28nm, you will play a key role in advancing the company's cutting-edge projects. Key Responsibilities: - Design and develop analog layout IP blocks and full-chip integration - Perform and resolve LVS/DRC violations independently - Collaborate with circuit design teams to optimize layout quality and performance - Ensure layouts meet design matching and parasitic constraints - Work with advanced nodes like 7nm, 16nm, and 28nm Required Skills: - 3+ years of relevant Analog Layout experience - Proficiency in LVS/DRC checks and EDA tools - Experience with lower technology nodes (3nm, 5nm, 7nm, 10nm, 16nm, 28nm, etc.) - Good understanding of layout matching, parasitic extraction, and floor planning - Strong verbal and written communication skills - Ability to work independently and within cross-functional teams In this role, you will be a Circuit Design Engineer at ARF Design, working on the design of building blocks used in high-speed IPs such as DDR/LPDDR/HBM/UCIe/MIPI/PCIe. You will derive circuit block-level specifications from top-level specifications and perform optimized transistor-level design of analog and custom digital blocks. Running SPICE simulations to meet detailed specifications and guiding layout design for best performance, matching, and power delivery will be part of your responsibilities. You will also characterize design performance across PVT + mismatch corners and conduct design reviews at various phases/maturity of the design. Qualifications: - BE/M-Tech in Electrical & Electronics - Strong fundamentals in RLC circuits, CMOS devices, and digital design concepts (e.g., counters, FSMs) - Experience with custom design environments (e.g., Cadence Virtuoso, Synopsys Custom Design Family) and SPICE simulators - Collaborative mindset with a positive attitude If you have 3+ years of experience and possess the required skills, please share your updated resume [Name_Post_Exp] to divyas@arf-desgn.com. This is a full-time, permanent position located in person at Bhubaneswar and Ranchi.,

Are you passionate about ensuring silicon design accuracy and power integrity at advanced nodes? We re looking for a skilled PDV & Power Analysis Engineer to join our growing team! Key Responsibilities: -Physical design verification and power analysis using Calibre, Innovus, and Voltus -Hands-on layout edits in Innovus and deep analysis of IR/EM reports from Voltus -Expertise in understanding and resolving DRC violations using Calibre and Innovus -Strong knowledge of IR drop and electromigration issues and their resolution -Scripting proficiency in TCL, AWK, and Python -Exposure to ADI flows and power domain-based designs is a strong advantage Who Should Apply: Engineers with a strong background in PDV and power integrity, comfortable working with industry-standard EDA tools and scripts, and who thrive in a collaborative environment.

Overview Keysight is on the forefront of technology innovation, delivering breakthroughs and trusted insights in electronic design, simulation, prototyping, test, manufacturing, and optimization. Our ~15,000 employees create world-class solutions in communications, 5G, automotive, energy, quantum, aerospace, defense, and semiconductor markets for customers in over 100 countries. Learn more about what we do. Our award-winning culture embraces a bold vision of where technology can take us and a passion for tackling challenging problems with industry-first solutions. We believe that when people feel a sense of belonging, they can be more creative, innovative, and thrive at all points in their careers. Responsibilities Looking for a ECE engineer with C/C++/Python coding skills to work on various Foundrykits automation and design projects. Immediate projects include (not limited to): Refactoring of python-based automation suite to develop common framework (module-based feature execution) Python Based EM Automation suite development Development of customized python-based EM Automation script for various foundries (eg. TSMC, Intel Foundry & TowerSemi) EM Qualification for Global Foundries, TSMC, Samsung, various nodes Qualifications - Bachelors/ Masters in Engineering with atleast 5 years of relevant experience - Excellent coding skills in C++/C/Python - Excellent Foundrykits design knowledge - Excellent hands-on experience using EDA tools especially EM tools - Have been a device modeling/ PDK engineer Careers Privacy StatementKeysight is an Equal Opportunity Employer.Looking for a ECE engineer with C/C++/Python coding skills to work on various Foundrykits automation and design projects. Immediate projects include (not limited to): Refactoring of python-based automation suite to develop common framework (module-based feature execution) Python Based EM Automation suite development Development of customized python-based EM Automation script for various foundries (eg. TSMC, Intel Foundry & TowerSemi) EM Qualification for Global Foundries, TSMC, Samsung, various nodes

Need to work in collaboration with global analog teams across sites. Will be responsible for driving innovation in Analog IP designs. Responsible for design of IPs like Voltage regulators, LDO, Current and Voltage reference, High Voltage charge pumps, temperature sensors, oscillators etc using industry standard EDA tools. Should provide technical leadership and mentor junior engineers. Responsible for developing processes and robust design methodology. Help build overall competency in Analog domain. Qualifications Bachelor or Master Degree in Electrical/Electronic Engineering with 12+ years of experience in Analog design across different technologies. Should have experience in developing analog IPs like Switch capacitor circuits, LDO, DC-DC converter, oscillator, ADCs, Should have experience in integrating Analog IPs in a complex system. Knowledge of PCB and system design will be preferred. Should experience in silicon characterization and probing. Should have experience in a multi-site environment, interacting with teams in other sites. Should possess good mentorship skills. Ability to coordinate priorities and initiatives

We are looking for an experienced Analog Layout Engineer with 8+ years of hands-on experience in full custom layout of analog and mixed-signal blocks. The ideal candidate should have expertise in advanced CMOS technologies and be capable of delivering high-quality layout from specifications to tape-out. Key Responsibilities: Execute full custom layout for analog/mixed-signal blocks (OpAmps, Bandgaps, LDOs, ADCs, etc.) Floorplanning, device matching, parasitic optimization, and electromigration compliance Perform DRC/LVS/ERC checks and work closely with verification teams Collaborate with circuit designers to optimize performance and area Ensure quality layout delivery in accordance with tape-out schedules Support post-layout simulation and debug efforts Requirements: 8+ years of experience in analog/custom layout Strong understanding of matching, shielding, and analog layout best practices Hands-on experience with layout tools (Virtuoso, IC Compiler, Calibre, etc.) Knowledge of various technology nodes (180nm to FinFET) Good communication, teamwork, and problem-solving skills Apply Now! If you meet the above qualifications and are ready to take on this exciting challenge, we would love to hear from you. Share your resumes at info@silcosys.com

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the worlds most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ Job Description: We are seeking a highly experienced and innovative Fellow to join our Physical Design (PD) Methodology team. The successful candidate will be responsible for driving advancements in PD methodologies, strategies, and tools to optimize the design and implementation of our semiconductor products. This role requires a deep understanding of physical design, EDA tools, and the ability to partner with cross-functional teams to achieve state-of-the-art design efficiency and performance. Key Responsibilities: Drive PD Methodology Innovations: Lead the development and implementation of cutting-edge physical design methodologies to enhance design efficiency, performance, and manufacturability. Strategic Planning: Develop and execute strategies that align with industry trends and company goals. Provide strategic direction for PD-related projects and initiatives. Methodology Development: Create and refine methodologies for physical design, including floorplanning, placement, routing, and timing closure. Ensure these methodologies are integrated into the design and development processes. End-to-End Design Optimization: Oversee the entire physical design process from initial concept to tape-out. Ensure design efficiency and performance are maintained throughout the product lifecycle. Cross-Functional Collaboration: Work closely with RTL design teams, verification teams, and other engineering groups to integrate physical design methodologies across all levels of the system. Vendor Engagement: Collaborate with EDA tool vendors such as Synopsys and Cadence to ensure tools meet our design requirements. Drive joint development efforts and influence tool enhancements. Tool and Flow Automation: Lead efforts in the development and optimization of EDA tools for physical design. Work with tool vendors to ensure the tools meet our design requirements. Signoff Enablement: Ensure that all physical design methodologies and processes meet signoff criteria for manufacturability and performance. Technology and Library Enablement: Work with technology and library teams to enable new technologies and libraries in the physical design flow. PPA Optimization Guidance: Provide guidance on optimizing power, performance, and area (PPA) during the physical design process. Debug and Support: Lead efforts in debugging design issues and providing support to design teams to resolve complex physical design challenges. Industry Engagement: Stay abreast of the latest advancements in physical design within the semiconductor industry. Represent the company in industry forums, conferences, and collaborations to influence and adopt best practices. Cross-Functional Leadership: Collaborate with various teams, including design, verification, software, and product management, to ensure physical design goals are met. Provide technical guidance and mentorship to team members. Innovation and Research: Foster a culture of innovation by encouraging research and experimentation in physical design techniques. Identify opportunities for patents and publications. Metrics: Define and track key performance indicators (KPIs) related to physical design efficiency and performance. Report on progress and impact to senior leadership. Qualifications Education: Ph.D. or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Experience: Minimum of 20 years of experience in physical design, EDA tools, or related areas. Proven track record of driving PD methodology innovations and strategies in a leading semiconductor company. Technical Expertise: Deep understanding of physical design, EDA tools, and design optimization techniques. Proficiency in relevant tools and technologies. Publications and Patents: Demonstrated history of publications in reputable journals and conferences. Experience with filing and securing patents related to physical design and EDA tools. Leadership Skills: Strong leadership and team management skills. Ability to lead cross-functional teams and drive complex projects to successful completion. Communication: Excellent verbal and written communication skills. Ability to articulate complex technical concepts to diverse audiences. Industry Knowledge: In-depth knowledge of industry trends, standards, and best practices in physical design for semiconductors Notice Period 2 Month or less

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the worlds most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ We are seeking a highly skilled and innovative Physical Design Specialist to join our team. The successful candidate will be responsible for troubleshooting critical issues, providing independent analysis, and generating data points to identify potential failures in the physical design of our semiconductor products. This role requires a deep understanding of CPU Cores physical design, EDA tools, and the ability to offer unbiased opinions and solutions to complex design challenges. The Physical Design Specialist will play a crucial role in bridging the gap between PD methodology and PD execution teams, ensuring execution excellence. Key Responsibilities: Critical Issue Resolution: Identify and resolve complex physical design problems during dry runs and execution. Provide independent analysis and solutions to critical issues impacting design integrity and performance, including challenges specific to CPU core physical design such as timing closure, optimization, and signal integrity Securing Execution Excellence: Ensure high standards of execution excellence by providing strategic guidance and support to the PD execution team. Monitor and evaluate the effectiveness of physical design processes and methodologies, ensuring optimal performance and power efficiency for CPU cores Bridging Methodology and Execution: Act as a liaison between the PD methodology team and PD execution team to ensure seamless integration of methodologies into practical execution. Facilitate communication and collaboration between teams to address challenges and optimize design processes for CPU core designs Data Analytics Generate and analyze data points to identify potential design failures and areas for improvement. Use advanced tools and techniques to predict and mitigate risks, focusing on CPU core-specific issues like floorplanning, placement, and routing Independent Review and Opinions: Conduct thorough and independent reviews of design methodologies and flows. Offer unbiased opinions and recommendations based on extensive experience and expertise in CPU core physical design strategies Mentorship and Guidance: Mentor and guide design teams on best practices and innovative solutions and share insights and knowledge to enhance team capabilities. Communication: Communicate findings and recommendations effectively to stakeholders and higher management, emphasizing CPU core design considerations Qualifications Education: Ph.D. or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Experience: Minimum of 20 years of experience in physical design, EDA tools, or related areas. Proven track record of driving PD methodology innovations and strategies in a leading semiconductor company. Technical Expertise: Deep understanding of physical design, EDA tools, and design optimization techniques. Proficiency in relevant tools and technologies. Publications and Patents: Demonstrated history of publications in reputable journals and conferences. Experience with filing and securing patents related to physical design and EDA tools. Leadership Skills: Strong leadership and team management skills. Ability to lead cross-functional teams and drive complex projects to successful completion. Communication: Excellent verbal and written communication skills. Ability to articulate complex technical concepts to diverse audiences. Industry Knowledge: In-depth knowledge of industry trends, standards, and best practices in physical design for semiconductors. Why Join Us Innovative Environment: Be part of a team that is at the forefront of physical design methodology innovations. Impactful Work: Contribute to the development of cutting-edge technologies that shape the future of semiconductor design. Collaborative Culture: Work with a diverse and talented team of professionals who are passionate about technology and innovation. Career Growth: Opportunities for professional development and career advancement in a dynamic and growing company. Notice Period 2 Month or less

THE ROLE: As a member of the EPIC server soc team , you will help bring to life cutting-edge designs.?As a member of the Physcial design/soc integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBILITIES: Working on Constraints, Full chip netlist generation, static timing analysis setup and signoff of multi-corner multi-voltage designs. Owning timing execution to meet timing requirements including timing budgeting, repeater planning, constraints/exceptions generation and management Areas of focus include Constraints generation, verification, Timing analysis and verification,extraction and noise glitch analysis Engaging closely with Design teams to understand the design, constraints and convergence challenges and providing ECOs with a focus on PPA and TAT optimizations. Hierarchical timing analysis and convergence at block, section and fullchip level. PREFERRED EXPERIENCE: 10+ years of professional experience in Constraints generation, Synthesis,STA, full chip timing and physical design, preferably with high performance designs. Demonstrated ability in areas of Timing analysis, timing convergence, SI/Noise analysis, Signoff quality (PVT, process variation effects, guardbanding, etc), Timing ECOs, PV/Noise modelling, .libs, is a must. Multi-voltage scenarios design handling knowledge is expected. STA closure/convergence execution on Low power designs is an added advantage. Expertise in industry standard EDA tools (Primetime) and ASIC design flow is required. Hands-on experience with Physical Design implementation is a plus Proficiency in scripting language, such as, Perl and Tcl. Versatility with scripts to automate design flow, analysis Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in16/14/10/7/5nm nodes Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Bachelors orMastersdegree in computer engineering/Electrical/Electonics and communication Engineering

THE ROLE: The focus of this role in the AECG ASIC organization is to own physical design implementation for next generation ASICsthat meet Engineering, Business and Customer requirements. Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player. THE PERSON: AMD is looking for an engineering leader passionate about driving the best Power Performance Area (PPA) of ASIC solutions for AECG customers. The ideal candidate will have proven experience in driving physical design optimization to deliver industry leading performance/area and performance/power. In this role the candidate will work with the customer, SOC architects, the CAD team and the design team and drive floorplanning and physical design flows for best in class ASIC solutions. KEY RESPONSIBILITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR, Formal Equivalence Handling different PNR tools - Synopsys Fusion Compiler, ICC2, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Cadence Genus, Innovus Provide technical support to other teams PREFERRED EXPERIENCE: 5+ years of professional experience in physical design, preferably ASIC designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Strong analytical/problem solving skills and pronounced attention to details ACADEMIC CREDENTIALS: Bachelors orMastersdegree in computer engineering/Electrical Engineering

THE ROLE: The focus of this role in the AECG ASIC organization is to lead physical design for next generation ASICsthat meet Engineering, Business and Customer requirements. Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player. THE PERSON: AMD is looking for an engineering leader passionate about driving the best Power Performance Area (PPA) of ASIC solutions for AECG customers. The ideal candidate will have proven experience in driving physical design optimization to deliver industry leading performance/area and performance/power. In this role the candidate will work with the customer, SOC architects, the CAD team and the design team and drive floorplanning and physical design flows for best in class ASIC solutions. KEY RESPONSIBLITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR, Formal Equivalence Deft at Handling different PNR tools - Synopsys Fusion Compiler, ICC2, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Cadence Genus, Innovus. Tasks to includeFull Chip Level Floor planning, Bus / Pin Planning, feed-thru planning, Clock Tree Synthesis, Placement, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, Physical Verification and Sign Off Identify complex technical problems, break them down, summarize multiple possible solutions, Drive and hands-on flow development and scripting PREFERRED EXPERIENCE: 8+years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: BS or MS degree in in Electrical Engineering or Computer Science. 8years of experience in physical design role leading to an understanding of RTL to GDS development.

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SMTS SILICON DESIGN ENGINEER THE ROLE: As a member of the Radeon Technologies Group, you will help bring to life cutting-edge designs.?As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Implementation and verification of DFT architecture and features Scan insertion and ATPG pattern generation ATPG patterns verification with gate-level simulation Test coverage and test cost reduction analysis Post silicon support to ensure successful bring up and enhance yield learning PREFERRED EXPERIENCE: Understanding of DesignforTest methodologies and DFT verificationexperience (eg.IEEE1500, JTAG 1149.x, Scan, memory BISTetc.) Experience with Mentortestkompressand/or SynopsysTetramax/DFTMAX Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design ACADEMIC CREDENTIALS: Bachelors orMastersdegree in computer engineering/Electrical Engineering.

As a Senior Hardware Design Engineer at Agnisys, you will have the opportunity to work on high-tech semiconductor products by joining our R&D team. We provide a progressive and innovation-driven environment that promotes constant learning, which is crucial for personal and professional growth. Basic Requirements: - A B.Tech degree in Electronics and Communication Systems - Proficiency in Verilog, VHDL, SystemVerilog & C - Experience with FPGA, EDA Tools, Linux, Perl, and Tcl - Excellent communication skills - Ability to work independently with minimal supervision and collaboratively within a team - Strong multi-tasking skills - Self-motivated with a solid team spirit Job Responsibilities: - Design, plan, document, and develop new hardware products from initial requirements to production-ready prototypes - Maintain existing designs and create new variants to incorporate new features and manage component end-of-life issues - Collaborate with Hardware team members, Product Management, Software Engineering, and Manufacturing to deliver reliable and standards-compliant products About Agnisys: Agnisys Inc. is a prominent supplier of Electronic Design Automation (EDA) software aimed at addressing complex design and verification challenges in system development. Our products facilitate a unified specification-driven development flow, enabling users to describe registers and sequences for SoC and IP projects and automatically generate RTL design, UVM testbenches, C/C++ embedded code, and documentation. This approach accelerates design, verification, firmware, and validation processes. Leveraging patented technology and user-friendly interfaces, our specification automation tools enhance productivity, efficiency, and accuracy in system design and verification. Established in 2007, Agnisys is headquartered in Boston, Massachusetts, with R&D centers in Milpitas, CA, and Noida, India. Location: Noida Job Type: Full-time Schedule: Monday to Friday Work Location: In person,

You are a highly experienced hardware board design engineer with a minimum of 5 years of experience. In this role based in Vadodara, India, you will be responsible for designing hardware boards, demonstrating strong systems knowledge, and the ability to understand high-level concepts efficiently to produce effective results. Your key responsibilities will include working on various stages of hardware product development cycles, specializing in high-speed board design, and demonstrating expertise in protocols such as PCIe, USB3.0, MIPI CSI/DSI, LVDS, HDMI, DDR3/4, SD/eMMC, NAND, SPI/I2C. You should have hands-on experience with peripherals like Image sensors, LCD displays, and flash memory, among others. Additionally, you must possess a good understanding of timing, pre and post signal integrity analysis, and simulation tools. Furthermore, you will be expected to have a solid background in board power supply design, including switching and linear regulators, power supply filtering, and knowledge of board design guidelines and EMI/EMC aspects. Your role will also involve board bring-up, functional testing, DVT measurements, and validation, utilizing tools like Cadence Orcad, Allegro, Visio, and Altium. As a successful candidate, you should be proficient in board level testing and adept at using lab instruments such as function generators, oscilloscopes, and multimeters. An understanding of board mechanical fitment, excellent analytical skills, and strong problem-solving abilities are essential. Moreover, you must be a collaborative team player capable of effective communication with cross-functional teams. A&W Engineering Works, the organization you will be joining, is dedicated to developing and implementing innovative solutions to real-world challenges. The company's expertise spans hardware, software, mechanical, and system development, with a focus on fast prototyping and delivering quick proof of concept while preparing for production. To apply for this position, please send your resume and cover letter to [email protected], ensuring to include the job title in the subject line.,

Qualification: B.E Electrical Responsibilities: Designing of Cables Harness Assemblies, Developing Electrical Interface Schematic and Interconnect involving electrical control panel parts, OEM power supplies, Protection Circuits, Control Circuits. Selections of OEM parts for the design. Preparing Drawings, engineering specification documents and Bom creation for C&H assemblies. Skills Requirement: Hands on experience in Electrical components selections (Control panel components), Circuit Sizing, Connectors and Cables for Harness assemblies based on Cable assembly application. Should have hands on experience on developing Electrical schematics, Interconnects, Cable and Harness design using E3S/ EPLAN/ tool. Working knowledge in various UL508, CE, IPC standards used by Electrical & Cable industry. Should have understanding of different methods of Plant / Process Automation. Additional Skills having advantages: Working experience with Supplier / Vendors for resolving issues. Knowledge on Uni-Graphics and 3D cable routing. Familiar with Team center Engineering PLM Already worked in Engineering Change Management atmosphere. Executed projects working with North American groups. Preferred Industry: Design Engineer in machine tool industry / Automotive Ancillary / Aerospace

As a skilled professional in Standard Cell Library Development, you will leverage your hands-on experience and expertise to contribute effectively to the characterization processes. Your solid understanding of CMOS and FinFET technologies will be key in ensuring the success of the projects at hand. Additionally, exposure to Verilog modeling will be advantageous in this role, although it is not mandatory. Your role will require strong debugging and problem-solving skills specifically related to cell design, SPICE simulation, and characterization. This will enable you to address challenges effectively and ensure the quality of the developed libraries. Proficiency in EDA tools is essential for this position. Experience with tools such as Cadence Virtuoso, Calibre, HSPICE, and other industry-standard simulation and characterization tools will be beneficial in carrying out your responsibilities efficiently. Overall, your role will be crucial in contributing to the development of Standard Cell Libraries, and your expertise will play a vital part in the success of the projects.,

You should hold a Bachelor or Master of Science degree in Electrical or Electronics engineering, Physics, or a related discipline. With a minimum of 5 years of experience, you must possess knowledge and expertise in the semiconductor field and analog domain. Your familiarity with EDA tools associated with Analog front-end from Cadence will be crucial for this role. Your responsibilities will include analog circuit design and simulations, requiring excellent written and verbal communication skills in English. Additionally, you should be adept at working in a dynamic environment, with strong analytical and problem-solving abilities. You will also be expected to drive discussions and meetings, as well as coordinate and track follow-up actions effectively. Experience with VerilogA and C coding is considered a plus for this position. The location for this opportunity is in Noida, and the ideal candidate should have a minimum of 5 years of relevant experience with a notice period of 0-30 days.,

As a Non-Volatile Engineering (NVE) Product Engineer at Micron Technology, Inc., you will be a key player in the Mask Design Development team, contributing to the Design for Manufacturability (DFM) process for new designs. Your role involves ensuring the timely delivery of high-quality mask designs by collaborating with cross-functional teams, enhancing DFM capabilities, and improving design methodologies for better manufacturability and performance of NAND products. Your responsibilities will include integrating DFM best practices into the design process, developing and enhancing DFM capabilities and tools, providing feedback to the NAND Design team based on DFM and manufacturing experience, and incorporating learning into continuous improvement efforts. You will also support test chips and early-stage development, own test chip activities, and build relationships across the organization through innovation forums. Additionally, you will collaborate with Quality teams to engage in reliability activities related to Reliability Sensitive Circuitry (RSC) and Design Failure Modes and Effect Analysis (DFMEA). You will act as a Quality representative, driving corrective and preventive actions to enhance mask design robustness and reliability. Micron Technology is committed to fostering a team culture where you can develop your skills, make a meaningful impact, and explore interests that contribute to your career growth. We prioritize having fun, caring for each other, and supporting one another. We are looking for an Engineer with a Bachelor's or Master's degree in Electronics Engineering, Microelectronics, Semiconductor Physics, or a related field, along with at least 8 years of experience in mask design, DFM methodologies, semiconductor design, and manufacturing. Strong understanding of semiconductor fabrication processes, lithography techniques, and familiarity with EDA tools such as Cadence for mask design and Verification tools like Calibre DRC, LVS, Net Extraction are essential. Effective problem-solving skills, the ability to work in a fast-paced collaborative environment, and excellent communication skills are also required. Micron Technology, Inc. is a global leader in memory and storage solutions, driving innovation to transform how information enriches lives worldwide. Through a focus on customer needs, technology leadership, and operational excellence, Micron delivers high-performance DRAM, NAND, and NOR memory and storage products under the Micron and Crucial brands. Our innovations power the data economy, enabling advancements in artificial intelligence, 5G applications, and more, from data centers to the intelligent edge. For more information, please visit micron.com/careers. If you require assistance with the application process or need reasonable accommodations, please contact hrsupport_india@micron.com. Micron strictly prohibits the use of child labor and complies with all relevant laws, regulations, and labor standards.,

B.E./B.Tech or M.E./M.Tech in Electrical/Electronics Engineering or Physics5+ years of hands-on experience in analog circuit design and EDA toolsStrong command over circuit simulation, layout porting, and analog front-end development Required Candidate profile Develop and support new design/technology porting flows Collaborate with PDK, Modeling, and Device teams Enable and validate schematic layout porting, set up analog simulations

We re Hiring: Sales Engineer Locations: Delhi / Pune / Bangalore Qualification: B.E./B.Tech in Electronics or Mechanical Engineering Experience: 5 10 Years CTC: Open to budget Travel: 70 75% (primarily across defense/government zones) About the Role: Are you passionate about technology and defense innovationWe are looking for a skilled Sales Engineer to join our team and drive business across government and defense sectors. You ll be responsible for the full sales cycle from opportunity identification to closure while collaborating closely with our technical and service teams. Key Responsibilities: Identify and engage key accounts in Aerospace Defense. Understand customer needs and propose tailored product solutions. Deliver product presentations and live demos of EDA/MCAD/CAE tools. Collaborate with pre-sales and technical teams to design end-to-end solutions. Manage and grow defense accounts (especially in Southern India). Host seminars, webinars, and industry-focused sessions. What We re Looking For: 5 10 years of sales experience, preferably in Aerospace Defense. Deep understanding of: EDA tools : Siemens EDA, Cadence, Synopsys MCAD tools : Creo (ProE), UGNX, Catia, Solid Edge, SolidWorks, Inventor CAE tools : Ansys, Nastran, Adams, Altair Proven track record handling government or defense accounts. Strong knowledge of the complete sales cycle. Soft Skills That Matter: Strong interpersonal communication skills Team player with strong analytical and presentation abilities Self-driven, proactive, and resilient under pressure Comfortable working across diverse cultures Willingness to travel extensively Job Type: Full Time Job Location: Bangalore Delhi Pune Apply for this position Allowed Type(s): .pdf, .doc, .docx By using this form you agree with the storage and handling of your data by this website. ABOUT US WhatsApp us Follow Us Email Us Toll Free No Kindly fill the form to request a brochure Request a Brochure This field is for validation purposes and should be left unchanged. Lets Connect! Schedule a Free Consultation call with our HR Experts Mail List " " indicates required fields Company Name Describe Services In Detail Our team Will Reach You This field is for validation purposes and should be left unchanged.

Analog Layout Engineer Experience3 to 5 Years QualificationB.E / B. Tech / M.E / M. Tech ESSENTIAL DUTIES AND RESPONSIBILITIES: Candidate should have a strong knowledge on devices and process/fabrication technology. Should have work experience in 7nm, 10nm, 14nm, 16nm etc Good understating of Deep Submicron issues and layout techniques. Expertise on matching, parasitic reduction, ESD, DFM etc. Proficiency in use of below EDA tools for full custom layout and post-layout verification DRC/LVS/DFM etc. Cadence Virtuoso Layout editor (L/XL/GXL) Verification toolsAssura/PVS/Calibre/ Hercules Preferred Skills: Scripting Knowledge of perl/shell/skill are highly preferred Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas

Lead Analog Layout Engineer Experience8 to 10 Years QualificationB.E / B. Tech / M.E / M. Tech Essential Duties & Responsibilities: Candidate should have a strong knowledge on devices and process/fabrication technology. Should have work experience in 7nm, 10nm, 14nm, 16nm etc Good understating of Deep Submicron issues and layout techniques. Expertise on matching, parasitic reduction, ESD, DFM etc. Proficiency in use of below EDA tools for full custom layout and post-layout verification DRC/LVS/DFM etc. Cadence Virtuoso Layout editor (L/XL/GXL) Verification toolsAssura/PVS/Calibre/ Hercules Ability to handle a team Preferred Skills: Scripting Knowledge of perl/shell/skill are highly preferred Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas

Physical Design Engineer Experience 4-10 yrs Job Overview: Strong background of ASIC Physical DesignFloor planning, P&R, Extraction, IR Drop Analysis, Static Timing and Signal Integrity.. Hands-on experience on technology nodes like 5nm,7nm, 14nm, 10nm. Good knowledge of EDA tools from Synopsys, Cadence and Mentor Hands-on experience in floor planning, placement optimizations, CTS and routing. Hands-on experience in cadence or Synopsys tool (Encounter, ICC, PT/PTSI, TEMPUS, DC, RC, VOLTAS) Job Category VLSI (Silicon engineering) Job Location IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida

We are seeking a highly skilled and motivated Mixed Signal Verification Engineer to join our team with 8+ years of expeirence. As a Mixed Signal Verification Engineer, you will be responsible for developing and implementing testbenches, checkers, and tests using System Verilog. You will also play a key role in creating and utilizing real-numbered analog behavioral models in System Verilog/Verilog-AMS for verification simulations. Ownership of Analog/Mixed designs at the chip and/or block level will be an important aspect of this role. Responsibilities: Develop and build Mixed-Signal testbenches, checkers, and tests using System Verilog. Create and utilize real-numbered analog behavioral models in System Verilog/Verilog-AMS for verification simulations. Take ownership of Analog/Mixed designs at the chip and/or block level, ensuring successful verification. Good Understandingof GLS simulations Collaborate with design engineers to understand design tradeoffs and create high-level models for design analysis. Perform behavioral modeling for verification simulations to validate the functionality and performance of mixed-signal designs. Debug and resolve issues arising from verification simulations and work closely with the design team to address any design-related concerns. Stay updated with the latest advancements in mixed-signal verification methodologies and tools, and drive continuous improvement initiatives. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

We are seeking a skilled and motivated DDR5/SerDes Verification Engineer to join our organization. As a DDR5/SerDes Verification Engineer, you will be responsible for verifying and validating the functionality and performance of DDR5 memory subsystems and high-speed SerDes interfaces. In addition to strong DDR5 and SerDes verification expertise, knowledge and experience with sideband I2C and I3C protocols would be considered a plus. Candidate should have Design and implement advanced verification environments and test benches using SystemVerilog/UVM Experience4-10 Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore

Experience: 5 to 12 years Location: Bangalore : We are seeking a highly skilled Design Verification Engineer to join our team in Bangalore. The ideal candidate will have 5 to 12 years of experience in IP and SOC verification and possess a strong background in SystemVerilog (SV) and Universal Verification Methodology (UVM). This role specifically requires expertise in GLS (Gate-Level Simulation). Key Responsibilities: IP and SOC Verification Conduct IP and SOC verification activities to ensure the functionality and correctness of integrated circuits. SystemVerilog (SV) and UVM Proficiency Demonstrate strong knowledge of SystemVerilog and Universal Verification Methodology for efficient and effective verification processes. Gate-Level Simulation (GLS) Proficiency in Gate-Level Simulation is a mandatory requirement for this position. Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. 5 to 12 years of relevant industry experience in IP and SOC verification. Strong expertise in SystemVerilog (SV) and Universal Verification Methodology (UVM). Proficiency in Gate-Level Simulation (GLS). If you are a talented Design Verification Engineer with a passion for ensuring the reliability and performance of integrated circuits, we encourage you to apply. Join our dynamic team and contribute to the advancement of cutting-edge technology. Job Category VLSI (Silicon engineering) Job Type Full Time Job Location IndiaBangalore