492 Eda Tools Jobs - Page 12

As an ASIC Verification Engineer at our game-changing AI solutions company, you will be responsible for developing verification environments for modules, subsystems, top level, and FPGA. You will build models, checkers, and random test frameworks using SystemVerilog and UVM. Additionally, you will participate in Low power analysis (UPF), power estimation, and C modeling. Your role will also involve performing lint, CDC, code coverage, and functional coverage, as well as formal verification of modules using SVA assertions. To excel in this role, you should have experience in verifying complex subsystems and ASICs. You should be adept at building scalable verification environments from scratch...

About Tata Electronics: Tata Electronics, a wholly owned subsidiary of Tata Sons Pvt. Ltd., is at the forefront of building India's first AI-enabled state-of-the-art Semiconductor Foundry. The cutting-edge facility is dedicated to producing chips for a wide range of applications including power management IC, display drivers, microcontrollers (MCU), and high-performance computing logic. These chips cater to the increasing demand in sectors like automotive, computing, data storage, wireless communications, and artificial intelligence. Tata Electronics, being a subsidiary of the prestigious Tata group, aligns itself with the group's global mission of enhancing the quality of life in communitie...

As an Analog Layout Engineer with 3-5 years of experience in advanced semiconductor technologies (5nm and below), you will be responsible for executing full custom layout designs for high-speed analog and mixed-signal blocks. Your expertise in custom layout design, FinFET technology nodes, and EDA tools like Cadence Virtuoso and Calibre will be crucial in collaborating closely with circuit design teams to interpret and implement layout specifications. Your key responsibilities will include performing layout verification, ensuring compliance with foundry design rules and layout best practices, addressing issues related to electromigration, IR drop (EMIR), and layout-dependent effects, as well...

As an Analog Layout Engineer, you will be responsible for designing and implementing analog layout solutions. With 3 to 7 years of experience, you will be based in Ranchi, Jharkhand. Your key skills should include proficiency in LVS/DRC checks and EDA tools, along with experience in lower technology nodes. A strong understanding of layout analysis, floor planning, and matching techniques is essential for this role. This is a full-time, permanent position with the interview mode being virtual and in-person. The ideal candidate should be able to join immediately or within 45 days. Immediate joiners are preferred, and the budget for this position is open based on the candidate's skills and expe...

As a Physical Design Engineer at HCLTech, you will be responsible for performing Timing analysis, timing convergence, SI/Noise analysis, and ensuring Signoff quality in the designs. With a minimum of 7 years of experience, you will demonstrate proficiency in handling multi-voltage scenarios design and STA closure on Low power designs. Your familiarity with industry standard EDA tools like Primetime will be essential for success in this role. Hands-on experience in Physical Design implementation will be a valuable asset. You will be expected to utilize your skills in scripting languages such as Perl and Tcl for automation purposes. Knowledge of 16/14/10/7/5nm nodes, along with an understandin...

As an Electrical Design Engineering Manager in the Systems Integration Group (SIG) at Micron Technology, you will lead a team of electrical engineers in developing semiconductor manufacturing test equipment. Your responsibilities will include supervising a team of electrical design engineers, evaluating workloads, and prioritizing resources for developing new electrical designs. Collaborating with cross-functional teams, planning and implementing project deliverables, deriving PCB design specifications, designing analog circuits, and FPGA design using HDL will be crucial aspects of your role. Additionally, you will need to provide technical guidance to management, support prototype qualifica...

MIPS is looking for a highly experienced and motivated Engineering Manager to lead the CPU team. In this critical role, you will manage a team of skilled engineers dedicated to developing high-performance CPU cores based on the RISC-V architecture. Your responsibilities will include overseeing the entire RTL design lifecycle, ensuring technical excellence, innovation, and timely delivery. You will lead and mentor a team of microarchitecture and RTL design engineers focused on high-performance CPU core development. Your role will involve driving the design execution of CPU subsystems, meeting performance, power, area, and quality goals. You will be responsible for creating and refining microa...

As a Sr. Staff Software Development Engineer at Lattice, you will be part of a dynamic and energizing international community of engineers, designers, and specialists dedicated to developing cutting-edge programmable logic solutions. Our focus on research and development, product innovation, and exceptional customer service drives us to bring our total commitment and competitive spirit to every project. In this role, you will be accountable for various responsibilities, including familiarity and hands-on experience with DevOps principles such as CI/CD, Perforce/Github, and EDA tools. You will have the opportunity to innovate in GenAI applications and productivity automation, administer publi...

This role is for an STA Engineer to be a key contributor in the synthesis and static timing analysis of complex SoCs. The ideal candidate will have extensive experience in timing closure, I/O constraint development for industry-standard protocols, and hands-on experience with advanced technology nodes. Responsibilities Perform synthesis of complex SoCs at both block and top levels. Develop and write timing constraints for intricate designs, including those with multiple clocks and voltage domains. Lead post-layout timing closure for multiple tape-outs, including handling timing ECOs and achieving STA signoff. Develop I/O constraints for industry-standard protocols such as DDR1/2/3, SDR, LPDD...

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life's work, to amplify human creativity and intelligence. As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do their...

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life's work, to amplify human creativity and intelligence. As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do their...

We are looking for self-sufficient full-time software engineers with a strong desire to build high-quality, long-lasting workflows. The VLSI Productivity and Infrastructure team supports hundreds of chip design engineers by building internal tools and platforms that supercharge their everyday work. From build automation to machine learning, databases to web applications, and on-prem compute to cloud workloads, this team handles it all! Although every member of our team is multi-faceted, the focus for this role is on automating workflows for user-friendliness, maintainability, and extensibility. You will work closely with chip designers to thoroughly understand their daily work and help stand...

As a Staff Data Scientist at Micron Technology, you will play a crucial role in the Silicon Verification Data Science team. Your primary responsibilities will involve utilizing advanced data science and AI/ML techniques to enhance efficiency, automation, and innovation in Silicon Design Verification. Collaborating closely with hardware engineers, verification teams, and software developers, you will aim to optimize verification workflows, enhance coverage, and expedite time-to-market for cutting-edge semiconductor products. Your key duties will include developing AI and Data Science solutions to create state-of-the-art tools for silicon design verification and firmware validation. You will b...

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an enthusiastic and detail-oriented engineer passionate about analog and mixed-signal circuit design. With a strong foundation in CMOS technologies and a keen interest in deep submicron process challenges, you thrive in collaborative, fast-paced environments. You enjoy div...

Job Description Change the world. Love your job. Do you want to work for an organization that values your opinion Do you want to work for an organization where you can play a pivotal role in several different areas Look no further. As a Texas Instruments (TI) Systems Engineer, you will have the opportunity to work in a vibrant and dynamic team oriented environment with exposure to a variety of state-of-the art applications each day. Responsibilities May Include Research and create new product definitions, including developing business case proposals, product strategies and taking products to RTM Analyze key end-equipment in automotive, industrial, consumer and computing spaces to identify fu...

As a Systems Engineer at Texas Instruments (TI), you will have the opportunity to work in a vibrant and dynamic team-oriented environment with exposure to state-of-the-art applications daily. Your responsibilities will involve researching and creating new product definitions, analyzing key end-equipment in various sectors, negotiating IC development tradeoffs, and providing technical expertise for product ramp-up. You will also be involved in silicon system evaluation, application support, and troubleshooting customer issues through lab testing and schematic analysis. Furthermore, you will contribute to generating revenue plans, creating technical literature, and driving revenue growth throu...

You will be integrated into the Foundry IP Development team in Bangalore at GLOBALFOUNDRIES. Collaborating closely with various engineering teams worldwide, you will be responsible for developing layout for Standard Cell IPs to facilitate high-quality product designs based on Globalfoundries" advanced process nodes. Your main responsibilities will include: - Designing layout for Standard Cell IPs - Performing layout checks such as LVS, DRC, DFM, EMIR - Reviewing layouts and assisting other layout teams - Preparing design kits from the layout side, along with verification and validation - Providing support for layout automation and scripting - Taking initiatives for productivity improvements ...

As a Non-Volatile Engineering (NVE) Product Engineer at Micron Technology, Inc., you will be an integral part of the Mask Design & Tapeout Solutions team, dedicated to enhancing the quality and efficiency of NAND Memory Design through Custom Layout Design and Tapeout Management. In this role, you will be responsible for supporting New Design Development and managing Design Revisions across the Product Lifecycle. Utilizing your expertise as a Mask Design Engineer, you will implement DFM, Process Input, and Fab Feedback, collaborating with cross-functional teams to drive yield improvements and develop innovative Layout Design techniques. You will oversee the Design Library, ensuring the build,...

Job Description: Tessolve is looking for an experienced Physical Design Engineer to join our team in Bangalore. The ideal candidate will have a strong background in RTL to GDSII implementation, expertise in advanced process nodes, and hands-on experience with industry-standard tools for floor planning, placement, clock tree synthesis (CTS), routing, timing closure, and physical verification. Key Responsibilities: End-to-end physical design flow from RTL to GDSII at advanced technology nodes (7nm, 5nm, or below). Floor planning and Partitioning: Optimize chip area, power, and performance. Placement and CTS: Optimize standard cell placement, buffer insertion, and clock tree synthesis. Routing ...

Job Description: Tessolve is looking for an experienced Physical Design Engineer to join our team in Bangalore. The ideal candidate will have a strong background in RTL to GDSII implementation, expertise in advanced process nodes, and hands-on experience with industry-standard tools for floor planning, placement, clock tree synthesis (CTS), routing, timing closure, and physical verification. Key Responsibilities: End-to-end physical design flow from RTL to GDSII at advanced technology nodes (7nm, 5nm, or below). Floor planning and Partitioning: Optimize chip area, power, and performance. Placement and CTS: Optimize standard cell placement, buffer insertion, and clock tree synthesis. Routing ...

Job SummaryJob Description: Tessolve is looking for an experiencedPhysical Design Engineerto join our team in Bangalore. The ideal candidate will have a strong background inRTL to GDSII implementation, expertise in advanced process nodes, and hands-on experience with industry-standard tools forfloorplanning, placement, clock tree synthesis (CTS), routing, timing closure, and physical verification. Key Responsibilities: End-to-endphysical design flow from RTL to GDSIIat advanced technology nodes (7nm, 5nm, or below). Floorplanning and Partitioning: Optimize chip area, power, and performance. Placement and CTS: Optimize standard cell placement, buffer insertion, and clock tree synthesis. Routi...

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Interfacing with customers regarding digital reference flows, including Synthesis Floorplanning Clock tree synthesis Power planning Place and route Timing closure Creating baseline flows to be used by customers as starting point for digital implementation Performing digital place and route and sign-off on small customer designs Creating documentation PPA optimization Bachelors degree with at least 4+ years of design/EDA experience or Masters degree. Strong knowledge of Digital Design Fundamentals, Semiconductor Fundamentals and Static Timing Analysis Prior experience with ASIC digita...

As a Software Development Engineer at Lattice, you will be part of a dynamic and enthusiastic team working on cutting-edge programmable logic solutions. Your role will involve contributing to innovative GenAI applications, enhancing productivity automation, and collaborating closely with cross-functional teams to drive R&D and product innovation. Key Responsibilities: - Utilize DevOps principles, including CI/CD, Perforce/Github, and EDA tools to streamline development processes. - Explore and innovate around GenAI applications to enhance product offerings. - Manage public multi-cloud and private cloud administration for efficient operations. - Demonstrate expertise in working with FPGAs and...

You have hands-on experience in developing Analog Layout / IO layout design, with a good exposure to FinFet layouts in lower nodes. You are an expert in using the best and latest features of Cadence and Calibre DRC/LVS. Your expertise extends to dealing with ESD, LUP, antenna layout challenges, and analyzing/fixing EMIR issues. You are capable of working both independently and within a team to ensure that work is completed efficiently. Your strong communication skills allow you to collaborate effectively with global engineering teams. You possess the ability to handle Analog Layout Design, EDA Tools, DRC, LVS, Calibre, and FinFet. Additionally, you have knowledge in Cadence, Virtuoso, and Ph...

The Rivos Power team is seeking a highly motivated engineer to develop and strategically drive state-of-the-art power modeling and optimization across our CPU and SoC blocks.In this role, you will have the opportunity to work in an innovative, collaborative, and high-growth environment. The ideal candidate will possess in-depth experience in the full spectrum of silicon power reduction. This includes a foundation in solid power analysis, performance benchmarking, and design optimization at all levelsfrom microarchitecture and physical implementation to standard power-performance benchmarking. What You&aposll Do Model and analyze power consumption for various workloads on custom silicon, work...