86 Eda Tools Jobs

: 6 to 8 years of Semiconductor industry experience in Custom Mixed-Signal layout design with a bachelors degree in electrical/Electronic Engineering. Able to deliver Custom analog layouts independently from schematic to layout generation, estimating the area, optimizing floorplan, routing, and complete verification flows. Firsthand experience in critical analog layout design blocks such as Temperature sensor, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc. Good at LVS/DRC debugging skills and other verifications for lower technology nodes - 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence VLE/VXL, PVS, Assura and Calibre DRC/ LVS is necessary. Understanding layout effects on the circuit such as speed, capacitance, power, and area etc. Ability to understand design constraints and implement high-quality layouts. Multiple Tape out support experience and collaborating with cross functional teams will be an added advantage. Good people skills and critical thinking abilities to resolve the issue technically and professionally. Excellent communication. Responsible for timely execution with high quality of layout design. Multiple foundries experience is an added plus. Minimum Educational Qualification : Educational Bachelor's, Electrical or Electronics Engineering or equivalent Role And Responsibilities Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support. Perform layout verification like LVS/DRC/Antenna, EM, quality check and documentation. Responsible for on-time delivery of block-level/top-level layouts with acceptable quality. Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment. Guide junior team-members in their execution of Sub block-level layouts & review their work Should have good experience in working with cross-functional team. Ensure standard processes and procedures are followed to resolve all client queries. Handle technical escalations through effective diagnosis and troubleshooting of client queries Manage and resolve technical roadblocks/ escalations to timely deliverable with high quality. Troubleshoot all client queries in a user-friendly, courteous, and professional manner. Offer alternative solutions to clients (where appropriate) with the objective of retaining customers' and clients' business. Build people capability to ensure operational excellence and maintain superior customer service levels of the existing account/client. Contribute to effective project-management. Effectively communicating with engineering teams in different Geographical locations to assure the success of the layout project. Works in the area of Software Engineering, which encompasses the development, maintenance and optimization of software solutions/applications.1. Applies scientific methods to analyse and solve software engineering problems.2. He/she is responsible for the development and application of software engineering practice and knowledge, in research, design, development and maintenance.3. His/her work requires the exercise of original thought and judgement and the ability to supervise the technical and administrative work of other software engineers.4. The software engineer builds skills and expertise of his/her software engineering discipline to reach standard software engineer skills expectations for the applicable role, as defined in Professional Communities.5. The software engineer collaborates and acts as team player with other software engineers and stakeholders.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Exp : 3- 5 Yrs Position : Senior or Lead Expertise : Power fundamentals Good knowledge of PTPX Good knowledge of CLP Knowledge of design verification, RTL coding, synthesis, and physical design Protocol knowledge of , DDR, CHI, Cache, computer organization, bus protocol, Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age and this is where you come in. Join QCOM Technologies Inc Global Emulation(Prototyping) team delivering solutions for design of leading-edge wireless products. Qualcomm is leading 5G innovations ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. The Qualcomm Global emulation team is currently seeking a lead engineer role for our team doing development/validation of large scale FPGA emulation tools/flows/methodologies In this role, you will be working in multiple areas of SoC/IP prototyping flows and methodologies. Would also involve enabling execution teams doing SOC prototyping during their usage of the platform Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 4-7 years of experience working in FPGA Synthesis, Prototyping of SoCs & IPs Candidates are expected to have experience in: Prior work experience on Emulation/Prototyping Platforms (HAPS, VPS, Protium etc) Multi-FPGA prototyping flow, from RTL preparation to h/w implementation Proficient in analysis & debug of issue in Synthesis, Place and Route, Timing closure, Clocking. Hands on experience in FPGA h/w debug using probes/ILA Proficient in EDA tools like - Vivado, Synplify, Protocompiler, VPS, VCS/Verdi etc RTL coding and simulation Well versed with working in unix/linux environment, using GVIM/VI editors, shell scripting Strong debug skills, aptitude to learn and resolve complex issues Experience in one or more scripting language - TCL, Python, Perl, Shell etc Sound knowledge of: FPGA architecture preferably Xilinx (ultrascale), Vivado IP catalog Synthesis, Timing concepts and SDC constraints Prototyping concepts like - partitioning, pinmux

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Additional Additional Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 6+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience. OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 5+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience. OR PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience. Preferred Qualifications: 10 years of experience Strong understanding of CAD/EDA tools and methodologies. Strong experience scripting (Python, Perl) in support of design verification Hands on experience with regression systems, CI/CD, Revision Control System (git, perforce) workflow. Strong fundamentals in digital design verification methodologies and EDA tools. Knowledge of SOC architecture Experience with web programming (javascript, etc) and databases. Principal Duties and Responsibilities: Develop and implement advanced CAD flows and methodologies to verify critical high performance and low power CPU designs. Utilize scripting languages (python) to automate CAD/IT processes and increase efficiency. Collaborate with cross-functional teams to ensure successful integration of CAD flows. Stay up-to-date with cutting-edge technology, conduct thorough analysis of CAD tools and make improvements. Work closely with users to troubleshoot and resolve any issues that arise in tools, flows, environment, and infrastructure. Collaborate with external vendors to ensure timely delivery, integration, and deployment of CAD/EDA tools while driving them to improve efficiency and productivity. Define and implement new infrastructure capabilities that can be used to accelerate design and development. Level of Responsibility: Works independently with minimal supervision. Work with chip leads in support of design verification. Collaborate with chip leads to understand the design methodology. high-level requirements, determine other areas to support current or future designs that can benefit from automation and tooling. Provides supervision/guidance to other team members. Decision-making is significant in nature and affects work beyond immediate work group. Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc. Has a moderate amount of influence over key organizational decisions. Tasks do not have defined steps; planning, problem-solving, and pri

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Job Overview In this highly cross functional role, you will be part of the Global Design Enablement team responsible for various aspects of PDK development across Custom, Analog and RF technology nodes. As a member of the CAD team, you will be working closely with Custom, Analog & RF Engineering design community to develop & support customized tools and flows for Schematic & Layout design, Circuit Simulation, IP characterization, Custom/Analog P&R and transistor-level EM/IR flows. You will also have the responsibility to collaborate with our Foundry and EDA partners to deploy best-in class EDA tools and flows in addition to developing in-house productivity & QoR automation solutions for improving overall design methodology. Minimum Qualifications Bachelors or masters in electrical engineering, Computer Science, or related field. 6+ years of industry experience in CAD/EDA or PDK development Knowledge of Virtuoso suite of tools- Schematic, Layout, Analog Design Environment etc. Proficiency in one or more of the programming/scripting languages- , Python, Perl and TCL. Good understanding of CMOS fundamentals and Circuit Design Concepts Strong aptitude for programming and automation Good communication skills and ability to work collaboratively in a team environment Preferred Qualifications Familiarity with SPICE simulation tools (Hspice, SpectreX/APS, AFS/Solido SPICE , PrimeSim SPICE, ADS, GoldenGate etc.) Experience with Electromagnetic tools, like Peakview and EMX, is a plus. Knowledge of FinFet & SOI processes is a plus Educational RequiredBachelor's, Electrical Engineering

About Marvell . Your Team, Your Impact As a key CAD member of Marvell Central Engineering, you will play a leading role on developing next-generation automated design flow and its add-on tools. You will have the opportunity to use your design and CAD knowledge to participate in defining the whole organizations design infrastructure, methodology and workflows. What You Can Expect Develop and maintain E2E power optimization flow to address Marvell s various Business Units. Contribute to the deployment and support of these flows. Work in collaboration with the rest of the team to ensure optimal integration inside the overall CAD platform. Come-up with innovative solutions to ever-increasing design challenges. Keep up with process and tool evolutions. Interface with EDA vendors for optimal tool usage. What Were Looking For BS/MS in EE/CS with 4+ years of hands-on experience in Implementation flows Familiarity with the usage of industry standard implementation tools like Cadence Innovus, Synopsys Fusion Compiler and Conformal/Formality Low power etc.. Understand the concepts of power optimization and lower power Deep understanding of flow knobs to achieve the required PPA at block-level Utilize implementation knowledge to drive EDA tools to achieve low power Familiarity with UPF format IEEE 1801 and low power checks Knowledge of signoff flows (STA,EMIR) is a plus Demonstrate good analysis and problem-solving skills. Out-of-the-box thinking. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-AB3

Position: Mechanical Design Engineer (Creo- modeling & drafting -1) (CE35SF RM 3278) Shift timing : 9 to 6 pm Work Mode : Hybrid Relevant Experience : 3-5 years of experience with Creo software, design & development Education : Bachelor s in mechanical engineering Must have skills: Creo MODELING AND DRAFTING, Engineering fundamental, Interface between Creo and Altium, GD&T, DFA and DFM concepts in design Good to have skills: Altium, Excellent verbal & communication skills Job Description: Experience with Creo & Windchill integration Creating and updating 3D models and drawings Creo, Windchill, and interface between Creo and Altium. Basic product lifecycle management knowledge. Sheet metal and plastic-design & development. Good understanding of engineering fundamentals. Good understanding of GD&T, Stack up analysis Basic understanding of the manufacturing process Work with cross-functional teams Highly proficient in Creo tools (Concept development, drawings, modeling, assembly, etc.) Job Category: Automotive EDA tools Job Type: Full Time Job Location: Pune Experience: 3 - 5 years Notice period: 0-15 days

Lead design of analog/mixed-signal ICs (ADC/DAC, PLL, LDO/DCDC, IO Drivers). Oversee verification, layout compliance, cross-functional collaboration, and product support. Utilize EDA tools for design, simulation, and debugging. Required Candidate profile Experienced analog/mixed-signal IC designer (8+ yrs), adept in variation-aware design, verification, debugging, and product support. Strong in cross-functional collaboration. Masters in VLSI or ECE

Qualifications and Preferred Skills: BS, MS in Electrical Engineering, Computer Engineering or Computer Science. 8+ years and current hands-on experience in microarchitecture and RTL development . Proficiency in Verilog, System Verilog . Familiarity with industry-standard EDA tools and methodologies. Experience with large high-speed, pipelined, stateful designs, and low power designs. In-depth understanding of on-chip interconnects and NoC's. Experience within Arm ACE/CHI or similar coherency protocols. Experience designing IP blocks for caches, cache coherency, memory subsystems, interconnects and NoC's. Familiarity with RAS designs, QoS in fabrics, PCIe/IO is a plus. Experience with modern programming languages like Python is a plus. Excellent problem-solving skills and attention to detail. Strong communication and collaboration skills.

Engineering, Staff Engineer Noida, Uttar Pradesh, India Apply Now Save Category: Engineering Hire Type: Employee Job ID 11860 Date posted 06/03/2025 Share this job Email LinkedIn X Facebook Description * Candidate will be part of TCM Front End team. * Troubleshoot and validate TCM Front End flow for seamless usage of VCS FE OM * Verify standard and customized features / checks in TCM FE for seamless consumption of VCS OM. * Will be working with other local and global teams of TCM and VC SpyGlass * Verify and validate state-of-the-art EDA tools involving development of new and innovative algorithms. * Create test cases to test the developed feature. Skills Required * Strong knowledge of Front-end compilers and their flow * Ability to develop new software architecture and good leadership skills. * Good knowledge of Verilog, SystemVerilog & VHDL HDL. * Familiarity with ASIC design flow and the EDA tools and methodologies used therein. * Familiarity with multi-threaded and distributed code development. * Self-motivation, self- discipline and the ability to set personal goals and work consistently towards them in a dynamic environment will go far towards contributing to your success. * Quality focus - one who believes in quality and wants to make a difference. * Experience of production code development on Unix/Linux platforms. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Now Save Relevant Jobs Engineering, Sr Staff Engineer Noida, India Engineering Engineering, Staff Engineer Noida, India Engineering Application Engineering, Sr.Engineer Bengaluru, India Engineering

Engineering, Sr Staff Engineer Noida, Uttar Pradesh, India Apply Now Save Category: Engineering Hire Type: Employee Job ID 11861 Date posted 06/03/2025 Share this job Email LinkedIn X Facebook Description * Candidate will be part of TCM Front End team. * Design, develop, troubleshoot the core algorithms used in TCM Front End tool * Design and develop standard and customized features / checks in TCM FE for seamless consumption of VCS OM. * Will be working with other local and global teams of TCM and VC SpyGlass * Design and development of state-of-the-art EDA tools involving development of new and innovative algorithms. * Create test cases to test the developed feature. Skills Required * Strong knowledge of Front-end compilers and their flow * Ability to develop new software architecture and good leadership skills. * Fluent in C/C++ with extensive work experience in data-structures and algorithms. * Good knowledge of Verilog, SystemVerilog & VHDL HDL. * Excellent algorithm analysis skills and a good knowledge of data structures. * Familiarity with ASIC design flow and the EDA tools and methodologies used therein. * Familiarity with multi-threaded and distributed code development. * Self-motivation, self- discipline and the ability to set personal goals and work consistently towards them in a dynamic environment will go far towards contributing to your success. * Quality focus - one who believes in quality and wants to make a difference. * Experience of production code development on Unix/Linux platforms. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Now Save Relevant Jobs Engineering, Sr Staff Engineer Noida, India Engineering Engineering, Staff Engineer Noida, India Engineering Application Engineering, Sr.Engineer Bengaluru, India Engineering

Responsibilities: Build and guide a team of DFT engineers to deliver the architecture and the DFT deliveries towards SOC development. Engage with the RTL & physical design program management to plan and execute the DFT deliveries. Work with cross-functional teams (e.g., design, verification, test engineering) to integrate DFT features effectively. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise : At least 10+ years of experience in DFT implementation / methodology Strong understanding of digital design and test principles. Proficiency in DFT techniques, such as scan insertion, BIST, and Automatic Test Pattern Generation (ATPG), MBIST insertion Experience with EDA tools , Synopsys and Cadence &scripting languages (e.g., Python, TCL). Knowledge of IC design flows, verification tools, and fault models Ability to identify, analyze, and resolve testing challenges. Work effectively within multidisciplinary teams, communicating complex technical details clearly. Ensure thorough testing, comprehensive fault coverage, and alignment with industry standards. Technically lead/managed 10 - 15 DFT engineers to deliver DFT implementation on SOC Preferred technical and professional experience NA

We are hiring a CAD Automation Software Engineer (Frontend & Backend) with 10+ years of experience to deploy and support front-end tools, develop scripts for regression and debug flows, and collaborate with design, implementation, and verification teams. The candidate must be proficient in scripting (Python, Bash, C), Linux administration, and version control (Git/Mercurial). Experience in ASIC flows, CAD tools, and CI/CD setup is essential.

In fast changing markets, customers worldwide rely on Thales. Thales is a business where brilliant people from all over the world come together to share ideas and inspire each other. In aerospace, transportation, defence, security and space, our architects design innovative solutions that make our tomorrows possible. Senior Technical Lead - Design Optimization for FPGAs Essential Specifications: Masters / PhD in Electrical Engineering, Computer Science, or a related field with at least 10 years of experience on FPGA based designs, design optimizations and problem solving. Strong understanding of digital logic fundamentals and computer architecture. Proficiency in FPGA programming techniques. Experience with timing analysis and optimization for FPGA designs. Excellent skills in Verilog programming language. Experience using Vivado or Questa Sim EDA tools. Desirable Specifications: Knowledge of RISC-V architecture. Effective presentation skills to communicate complex ideas. Familiarity with verification techniques using UVM. Responsibilities: Work on a variety of design optimization problems for FPGA-based systems. Collaborate with the team to develop innovative solutions for performance improvement, power optimization, and area reduction. Implement designs using FPGA programming languages like Verilog. Conduct timing analysis and optimize designs to meet performance requirements. Utilize Vivado or Questa Sim EDA tools for design and validation. Stay informed about the latest advancements in FPGA design optimization. Document research findings and project progress accurately. Participate in team meetings, providing valuable insights and suggestions.

Job Summary: We HCL TECH are seeking a highly skilled Design Verification Engineer (DV) to join our growing team and play a vital role in ensuring the quality and functionality of our advanced ASICs and SoCs. This position requires a strong foundation in verification methodologies and the ability to handle complex verification tasks. You will be instrumental in developing robust verification plans and environments to guarantee the success of our next-generation integrated circuits. Responsibilities: Develop and implement comprehensive verification plans utilizing industry-leading methodologies (UVM, Formal Verification) Design and create high-quality verification environments (testbenches) to achieve exceptional code coverage Utilize advanced verification tools (simulators, formal verification tools) to thoroughly verify RTL functionality Debug and analyze verification failures with a keen eye to identify and resolve the root cause of design issues Collaborate effectively with RTL design engineers to ensure efficient bug resolution and verification plan adherence Lead and mentor junior DV engineers within the team, fostering a collaborative and knowledge-sharing environment Participate in code reviews and champion best practices for verification code quality Stay current with the latest advancements in verification tools and methodologies Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus) 4-10 years of solid experience in Design Verification for ASICs or SoCs In-depth knowledge of digital design principles (combinational logic, sequential logic, finite state machines) Proven ability to develop, debug, and optimize complex verification environments Expertise in Verilog or VHDL with a strong understanding of verification methodologies (UVM, Formal) Extensive experience with simulation tools (ModelSim, Cadence Incisive, Synopsys VCS) and scripting languages (Python, Perl) Experience with formal verification tools and techniques is a plus Excellent analytical and problem-solving skills with a meticulous attention to detail Strong communication, collaboration, and leadership skills to effectively contribute and guide the team Benefits: Competitive salary and benefits package commensurate with experience Opportunity to work on leading-edge technologies and projects with a high impact Collaborative and dynamic work environment that fosters continuous learning Potential for professional development and career advancement

Lead Analog Layout Engineer Experience8 to 10 Years QualificationB.E / B. Tech / M.E / M. Tech Essential Duties & Responsibilities: Candidate should have a strong knowledge on devices and process/fabrication technology. Should have work experience in 7nm, 10nm, 14nm, 16nm etc Good understating of Deep Submicron issues and layout techniques. Expertise on matching, parasitic reduction, ESD, DFM etc. Proficiency in use of below EDA tools for full custom layout and post-layout verification DRC/LVS/DFM etc. Cadence Virtuoso Layout editor (L/XL/GXL) Verification toolsAssura/PVS/Calibre/ Hercules Ability to handle a team Preferred Skills: Scripting Knowledge of perl/shell/skill are highly preferred Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul Singapore SwedenStockholm USADelaware USATexas Location - Bengaluru,Chennai,Hyderabad,Noida

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Interfacing with customers regarding digital reference flows, including Synthesis Floorplanning Clock tree synthesis Power planning Place and route Timing closure Creating baseline flows to be used by customers as starting point for digital implementation Performing digital place and route and sign-off on small customer designs Creating documentation PPA optimization Bachelor s degree with at least 1-3 years of design/EDA experience or Master s degree. Strong knowledge of Digital Design Fundamentals, Semiconductor Fundamentals and Static Timing Analysis Prior experience with ASIC digital implementation flows and EDA tools is required; Experience with advanced nodes (7nm and below) preferred. Good programming knowledge in Unix, Shell scripting, perl and importantly TCL Strong customer-facing communication and problem solving skills Strong personal drive for continuous learning and expanding professional skill sets Excellent verbal and written communication skills Familiar with EDA tool operation, setup and debug: Digital: Genus, Innovus, Tempus, Voltus, etc We re doing work that matters. Help us solve what others can t.

We are hiring a CAD Automation Software Engineer (Frontend & Backend) with 10+ years of experience to deploy and support front-end tools, develop scripts for regression and debug flows, and collaborate with design, implementation, and verification teams. The candidate must be proficient in scripting (Python, Bash, C), Linux administration, and version control (Git/Mercurial). Experience in ASIC flows, CAD tools, and CI/CD setup is essential.

We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: You are a seasoned engineer with a passion for pushing the boundaries of technology With 8-15 years of experience, you bring a wealth of knowledge in software architecture and leadership You excel in C/C++ software development, and your strong background in design patterns, data structures, and algorithms sets you apart You thrive in multi-threaded and distributed code environments, and your familiarity with ASIC design flow and EDA tools is second to none Your expertise in Verilog, SystemVerilog, and VHDL HDL, coupled with your experience in Unix/Linux platforms, makes you a valuable asset You are well-versed in developer tools like gdb and Valgrind, and you understand the importance of source code control tools such as Perforce Your analytical and problem-solving skills are top-notch, and you are always eager to learn and explore new technologies As a highly enthusiastic and energetic team player, you are ready to go the extra mile to achieve success, What Youll Be Doing: Designing, developing, and troubleshooting core algorithms for word-level synthesis Collaborating with local and global teams to enhance synthesis QoR, performance, and logic interference Engaging in pure technical roles focused on software development and architecture Implementing multi-threaded and distributed code solutions Utilizing your knowledge of ASIC design flow and EDA tools to drive innovation Leveraging your expertise in Verilog, SystemVerilog, and VHDL HDL to develop cutting-edge solutions, The Impact You Will Have: Driving technological innovation in chip design and verification Enhancing the performance and quality of synthesis tools used globally Solving complex logic interference problems to improve design accuracy Contributing to the development of high-performance silicon chips and software content Collaborating with cross-functional teams to achieve project milestones Pioneering new software architectures that set industry standards, What Youll Need: Strong hands-on experience in C/C++ based software development Deep understanding of design patterns, data structures, algorithms, and programming concepts Familiarity with multi-threaded and distributed code development Knowledge of ASIC design flow and EDA tools and methodologies Proficiency in Verilog, SystemVerilog, and VHDL HDL, Who You Are: Highly enthusiastic and energetic team player with excellent communication skills Strong desire to learn and explore new technologies Effective problem-solver with a keen analytical mind Experienced in working on Unix/Linux platforms Adept at using developer tools such as gdb and Valgrind, The Team Youll Be A Part Of: You will be part of the word-level synthesis team, catering to multiple EDA products This team focuses on developing innovative solutions to improve synthesis quality of results (QoR), performance, and logic interference You will work closely with both local and global teams to drive technological advancements and achieve project goals, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process,

Develop and maintain circuit design methodology flows and documentation. Identify and refine circuit implementations to achieve optimal power, area and performance targets. Propose design and verification strategies that efficiently use simulator features to ensure highest quality design. Oversee physical layout to minimize the effect of parasitic, device stress, and process variation. Collaborate with digital RTL engineers on the development of calibration, adaptation and control algorithms for analog circuits. Present simulation data for peer and customer review. Mentor and Review the progress of junior engineers. Document design features and test plans. Required Qualifications: Bachelor with 2 years experience or MSEE (or PhD) in Electrical Engineering, Computer Engineering, or similar technical field In-depth familiarity with transistor level circuit design - sound CMOS design fundamentals. Silicon-proven experience implementing circuits like bandgap references, voltage regulators. Detailed design experience with high custom logic design Experience optimizing FinFET CMOS layout to minimize the effect of parasitic resistance and capacitance, and to reduce the effects of local device mismatch and proximity effects. Awareness of ESD issues (i.e. circuit techniques, layout). and design for reliability (i.e. electro-migration, IR, aging, etc.). Experience with EDA tools for schematic entry, physical layout, and design verification. High proficiency with spice simulators including HSPICE, Finesim and XA Knowledgeable in Verilog-A and/or System-Verilog for analog behavioral modeling and simulation-control / data-capture. Plus Qualifications: Ability to provide automationfor rapid and dynamic design needs is highly sought-after Experience with STA and cell characterization such as Nanotime, Primetime, SiliconSmart Experienced in STAR or similar extractor to debug extraction issues Extensive programming skills in languages such as Python, Perl, TCL and C/C++

raja.a@honeybeetechsolutions.com resume 3+ years of hands-on experience in C++ development 12 years of working knowledge of Python scripting Prior experience in a Semiconductor company is mandatory Exposure to or hands-on use of EDA tools (e.g., Synopsys, Cadence, Siemens EDA) Strong problem-solving skills and understanding of software design principles Excellent verbal and written communication skills Bachelors or Masters degree in Computer Science, Electronics, or related field Domain Semiconductor Domain We are looking for a Software Engineer with a strong foundation in C++ programming and a working knowledge of Python scripting to join our high-performance engineering team. The ideal candidate will come from a semiconductor background and have experience working with EDA tools in a product or service environment. You will collaborate with cross-functional teams to develop, maintain, and optimize code critical to semiconductor design workflows. Your ability to communicate effectively and work in a fast-paced, innovation-driven setup will be key to your success in this role.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique One Cadence - One Team culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other every day. Job Summary: We are looking for a candidate with a strong technical background, impeccable communication skills (both written and verbal), and the ability to ramp up on new technologies quickly and independently. This is an excellent opportunity to work in a supportive and friendly work environment where we are vested in each other s success and passionate about technology and innovation. Job Responsibilities Understand electronic design automation (EDA) principles and related technical concepts, perform research, and translate the technical information into usable and practical product documents for consumption by Cadence customers. Work closely with subject-matter experts, including the development (R&D), product engineering, customer support, and product management teams, gain expertise in working hands-on with the EDA tools, and document new and enhanced software features, aligning with the release schedule. Understand and adhere to Cadence writing standards, develop topic-based (structured) content, and apply content taxonomy, and re-use strategies. Effectively use technical communications tools for authoring (FrameMaker, Wiki), screen capture/recording (SnagIT), video development (Captivate, Camtasia), and optionally graphic design (Photoshop). Coordinate with cross-functional teams in different geographies within Cadence and show a sound understanding of the product and documentation life cycle. Improve the product quality by reviewing product messages and UI. Develop supporting collateral, including feature videos and blogs. Experience A bachelors degree in any discipline (preferably computer science or electronics engineering) 3-4 years of experience in a technical communications or instructional design role, preferably in EDA, semiconductor industry, or other technical domains.

About The Role We are looking for a skilled CAD Engineer with expertise in Design Compiler (DC) and PrimeTime (PT) and TCL scripting to join our team The successful candidate will be responsible for developing and maintaining ASIC design flows, ensuring efficient and effective design processes. Key Responsibilities Develop and maintain CAD flows for ASIC design using Design Compiler (DC) and PrimeTime (PT). Create and optimize TCL scripts to automate design processes and improve workflow efficiency. Collaborate with design and verification teams to ensure seamless integration of CAD tools and methodologies. Troubleshoot and resolve issues related to CAD tools and design flows. Stay updated with the latest advancements in CAD tools and methodologies to continuously improve design processes. Qualifications Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field. 4+ Years of relevant expertise in CAD flow development for ASIC design. Proficiency in TCL scripting, particularly with Design Compiler (DC) and PrimeTime (PT). Strong problem-solving skills and the ability to troubleshoot complex design issues. Excellent communication and teamwork skills. Preferred Qualifications Experience with other EDA tools and scripting languages. Knowledge of digital design and verification methodologies. Familiarity with version control systems and collaborative development environments

Qualifications: Bachelor s or Master s degree in Electronics, Electrical Engineering, or a related discipline Proven experience in circuit design, analysis, and validation (analog, digital, mixed-signal) Proficiency with EDA tools (e.g., Altium Designer, KiCad, OrCAD, LTspice, Multisim, Fusion) Strong knowledge of measurement instruments and lab testing procedures (oscilloscopes, signal generators, etc.) Ability to diagnose and resolve complex hardware issues independently Excellent communication skills and ability to generate comprehensive technical reports

raja.a@honeybeetechsolutions.com resume 3+ years of hands-on experience in C++ development 12 years of working knowledge of Python scripting Prior experience in a Semiconductor company is mandatory Exposure to or hands-on use of EDA tools (e.g., Synopsys, Cadence, Siemens EDA) Strong problem-solving skills and understanding of software design principles Excellent verbal and written communication skills Bachelors or Masters degree in Computer Science, Electronics, or related field Domain Semiconductor Domain We are looking for a Software Engineer with a strong foundation in C++ programming and a working knowledge of Python scripting to join our high-performance engineering team. The ideal candidate will come from a semiconductor background and have experience working with EDA tools in a product or service environment. You will collaborate with cross-functional teams to develop, maintain, and optimize code critical to semiconductor design workflows. Your ability to communicate effectively and work in a fast-paced, innovation-driven setup will be key to your success in this role.