332 Eda Jobs - Page 14

Looking for PCB layout design Engineers with the following requirements: Hands-on experience in complex, high-density, high-speed PCBs, Analog, Digital, RF, mixed-signal PCB layout design. Hands-on experience with High-speed interfaces like DDR3,DDR4, LPDDR, , PROCESSORS, FPGA, PCIE, USB, SATA, MIL-1553, ADC, DAC, ETHERNET, NAND & NOR FLASH, SD, RS-422, BLUETOOTH 4.0, WIFI, GPS, GSM etc. Hands on Complex layout HDI designs with multiple BGAs and Multiple Fine pitch BGA (0.8mm and 0.5mm) of high pin count (2084 pins). Library creation as per IPC 7351 standard. Electrical Constrains setup for high-speed modules to match its requirement (Length match, impedance, delay tuning requirements) Exper...

We are seeking a seasoned Back-End Engineer with a strong foundation in Java , along with hands-on experience in data engineering within cloud environments. The ideal candidate will have a deep understanding of building scalable backend systems and working with modern data platforms such as Snowflake/ OpenSearch/AWS Glue . This role combines core backend development with data pipeline engineering to support both operational and analytical needs. Responsibilities: Backend Engineering: Design, build, and maintain scalable RESTful APIs and backend services using Java . Lead and contribute to the transformation of legacy platforms to Microservices and Event-Driven Architectures (EDA) . Participa...

Educational Requirements Bachelor of Engineering Service Line AI & Automation Service Line Responsibilities Responsibilities Anchor ML development track in a client project Data collection, profiling, EDA & data preparation AI Model development, experimentation, tuning & validation Present findings to business users & project management teams Propose ML based solution approaches & estimates for new use cases Contribute to AI based modules in Infosys solutions development Explore new advances in AI continuously and execute PoCs Mentoring – Guide junior team members & evangelize AI in organizationTechnical skills ProgrammingPython, R, SQL ML algorithmsoStatistical ML algorithmsoDeep Neural Net...

Data Engineer / Data Analyst (Hybrid Role) 10+ Yrs Data Analysis: Pandas, NumPy, SQL, EDA techniques Data Engineering: ETL pipelines, Airflow, Spark Cloud: GCP BigQuery, AWS Redshift Statistical Insight: Ability to assess data quality and completeness GoodTohave: Metadata & Standards: DCAT, schema.org, croissant Zero-Copy Architecture: Real-time data linking without duplication Data engineer, data analyst, Pandas, NumPy, SQL, EDA, Airflow, Spark, GCP, biq query, AWS, redshift

About BU- DoSelect DoSelect, part of the Info Edge (Naukri.com) group, is a leading skill assessment and talent intelligence platform trusted by 4,000+ global organizations. Founded in 2015 and headquartered in Bengaluru, we enable enterprises to make data-driven hiring and upskilling decisions through real-world, project-based assessments across 25+ programming languages, AI/ML, data science, and more. At DoSelect, you gain real-time, hands-on experience working with a diverse enterprise clientele, making it an ideal place to grow your skills and career in a dynamic HR tech ecosystem. Role Overview- We are seeking a motivated Python Data Science & AI Intern to join our technical content tea...

: To work independently on block/IP levels analog layout design from schematic. Estimating the Area, Optimizing Floorplan, Routing and Verifications. Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 5,7,10, 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence Virtuoso Editor & Calibre RVE Good interpersonal skills and critical thinking abilities to resolve the issue technically, and professionally. Key Responsibilities: Independently execute block/IP-level analog layout from schematics, including area estimation, floorplan optimization, routing, a...

: To work independently on block/IP levels analog layout design from schematic. Estimating the Area, Optimizing Floorplan, Routing and Verifications. Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 5,7,10, 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence Virtuoso Editor & Calibre RVE Good interpersonal skills and critical thinking abilities to resolve the issue technically, and professionally. Key Responsibilities: Independently execute block/IP-level analog layout from schematics, including area estimation, floorplan optimization, routing, a...