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11.0 - 15.0 years
11 - 15 Lacs
bengaluru, karnataka, india
On-site
Lead and develop timing methodologies, establish SDC constraints, and automate processes for special timing checks, ensuring design convergence and managing ECOs effectively. Perform static timing analysis setup and sign-off for multi-corner, multi-voltage processes to align with PPA targets, initially at the hierarchical level and subsequently at the top-level, reviewing the timing arcs for the .lib generation. Collaborate closely with RTL, DFT, and IP teams to ensure smooth integration and address physical design concerns affecting scan shift and scan capture modes for DFT. Identify opportunities to optimize clock skew and insertion delay across various corners and modes. Evaluate the cloc...
Posted 1 month ago
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