6 Eco Generation Jobs

As a Hardware Engineer at Qualcomm India Private Limited, you will be responsible for independent planning and execution of Netlist-to-GDSII. Your role will involve a good understanding of basics of static timing analysis and well-versed with Block level and SOC level timing closure (STA) methodologies, ECO generation, and predictable convergence. You will collaborate closely with design, DFT, and PNR teams to resolve issues related to constraints validation, verification, STA, Physical design, and more. Your exposure to high frequency multi-voltage design convergence and good understanding of clock networks will be essential for this role. Additionally, your circuit level comprehension of t...

As a Physical Design Engineer/Lead, with 5 to 15 years of hands-on experience, your role will involve the following key responsibilities: - Implementing block-level Physical Design from RTL to GDSII or Netlist to GDSII. - Conducting block-level Physical Signoff. - Ensuring block-level Timing Signoff and ECO generation. - Performing block-level Power Signoff. - Demonstrating proficiency in Automation tools such as Perl, Tcl, Awk, and Python. - Providing technical guidance to junior engineers and leading a team of 4-6 engineers. - Leading small project teams effectively. - Utilizing strong communication skills to be the single point of contact for clients. In this role, remote work is not avai...

As a Physical Design Engineer at eInfochips (An Arrow Company), your role will involve the following key responsibilities: - Implementing block level Physical Design from RTL to GDSII or Netlist to GDSII. - Conducting block level Physical Signoff. - Performing block level Timing Signoff and ECO generation. - Ensuring block level Power signoff. - Demonstrating strong skills in Automation using Perl, Tcl, Awk, and Python. - Providing technical guidance to Junior Engineers and leading a team of 4-6 engineers. - Leading small project teams effectively. - Excelling in communication skills as you will be the single point of contact for clients. Qualifications required for this role: - At least 3+ ...

As a Physical Design Engineer at UST, you will be responsible for the following: - Expected to be very good in Basic Fundamentals of C-MOS technology - Able to handle RTL/Netlist to GDSII independently at block level and should have done multiple tape outs (Low power implementation is preferred) - Hands-on experience of working on Lower technology nodes like 5nm, 7nm, 10nm, 14nm, 16nm, 28nm etc. - Proficient in floor planning, placement optimizations, clock tree synthesis (CTS), and routing - Experienced in block/top level signoff Static Timing Analysis (STA), physical verification (DRC/LVS/ERC/antenna) checks, and other reliability checks (IR/EM/Xtalk) - Expertise in industry standard EDA t...

You have a job opportunity for the Manager / Senior Role Physical Design Engineer position in Hyderabad. Your primary responsibilities will include: - Performing IP/Block level PnR activities from Netlist to GDS-II - Demonstrating good knowledge of all PnR activities such as Floor-planning, Placement, CTS, Routing, Timing closure (STA), and signoff checks like FEV, VCLP, EMIR, and PV - Executing all the Physical Implementation steps from Physical Synthesis to a Sign-Off GSD2 file - Handling signoff convergence, block-level Timing Signoff, ECO generation, and Power signoff - Having knowledge of high performance and low power implementation methods (preferred) - Expertise in ICC2/Fusion Compil...

As a Physical Design Engineer/Lead based in Noida, Ahmedabad, Bangalore, or Hyderabad, you will be responsible for leveraging your 5 to 15 years of hands-on experience in various aspects of physical design implementation. Your key responsibilities will include executing block-level physical design implementation from RTL to GDSII or Netlist to GDSII, ensuring block-level physical signoff, conducting block-level timing signoff and ECO generation, and overseeing block-level power signoff. Your role will also entail demonstrating proficiency in automation using tools such as Perl, Tcl, Awk, or Python. Additionally, you will be expected to offer technical guidance to a team of 4-6 junior enginee...