Design Verification Manager - 12+ Years @ Bangalore! Rajnehap Tech Services Hyderabad

12.0 - 20.0 years

25 - 40 Lacs

bengaluru

Hybrid

DV Manager: 12+ Years Location: Bangalore Notice: 0 - 15 Days Summary Senior technical leadership position responsible for ASIC/RTL design verification, team management, and implementation of verification strategies using advanced tools and methodologies. Key ResponsibilitiesResponsibilities 1 Lead and manage verification team of 10+ members (Must have) 2 Develop and implement verification strategies using System Verilog 3 Oversee OVM/UVM implementation and verification processes 4 Manage simulation environments across multiple platforms (Synopsys/Mentor Graphics/Cadence) 5 Drive scripting and automation initiatives 6 Lead debugging and analysis of complex digital design issues 7 Oversee verification of processor subsystems 8 Manage validation suite creation and automation 9 Guide silicon bring up and testing processes 10 Ensure quality and completeness of verification deliverables Qualifications & SkillsEducation B.E/B.Tech/M.E/M.Tech in Electrical/Electronic Engineering Experience 12+ years in ASIC/RTL design verification Skills: System Verilog Testbench Architecture, OVM, UVM expertise, Simulator tools (Synopsys/Mentor Graphics/Cadence), Scripting languages (Perl, Python, Shell, Tcl/Tk), Hardware verification languages (SystemVerilog, SystemC), Hardware description languages (Verilog, VHDL), AMBA, AHB, AXI, JTAG protocols, Gate-Level Simulation and Debugging, Processor subsystems (ARM/RISC), Silicon testing and bench application. Contact: 91 97041 22348 / hr@singhtechservices.com

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