1750 Drc Jobs - Page 8

Competitive Exams EdTech state PCS UPSC 9 (views) chandigarh Full Time Job role insights Date posted October 17, 2025 Hiring location chandigarh Career level fresher or Experienced Qualification Bachelor Degree Gender Any Gender Show more Hide less Description Open Positions: 📍 Location: 💼 Role & Responsibilities: Business Development Executive: Customer Support Representative: ✨ Requirements: 📩 How to Apply: 📢 We’re Hiring at Chetan Bharat Learning (CBL)! Chetan Bharat Learning , a leading educational platform, is looking for talented and motivated professionals to join our dynamic team in Chandigarh . If you’re passionate about growth, communication, and helping learners succeed — this is ...

Competitive Exams EdTech UPSC 58 (views) Gurugram Full Time Job role insights Date posted October 17, 2025 Hiring location Gurugram Career level fresher or Experienced Qualification Bachelor Degree Gender Any Gender Show more Hide less Description Job Description: Requirements: What We Offer: Forum IAS is Hiring - Prelims Reviewer (Full-Time) Location : Gurgaon Working Days : 6 days a week Shift Timings : 8.5 - 9 hours per day Candidates with 2 UPSC CSE mains can Apply. Job Description We are looking for a dedicated Prelims Reviewer to join our team in Gurgaon. The ideal candidate will be responsible for: Reviewing and evaluating prelims answer sheets with accuracy and attention to detail. P...

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Enginee...

As a Standard Cells Layout Design Engineer at Micron Technology, you will play a crucial role in designing and maintaining standard cells layout for new DRAM products on cutting-edge technology. Your responsibilities will include: - Leading standard cells layout projects from initial spec definition to PPA qualified library release - Collaborating closely with the DTCO team to develop standard cells architecture for emerging technologies - Performing layout verification tasks such as LVS, DRC, Latchup, quality checks, and documentation - Ensuring on-time delivery of block-level layouts with acceptable quality - Demonstrating leadership skills in planning, area/time estimation, scheduling, de...

He/She should be able to do block level / top-level floor planning, PG Planning, partitioning (for hierarchical designs) , placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks and be able to fix the violations . S hould have worked on 4 5nm , 28nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias. Provide technical guidance, mentoring to physical design eng inee rs. Interface with front-end ASIC teams to resolve issues. Excellent comm...

Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. PD JD: Thorough knowledge of the ASIC designs Place and Route flow and methodology. Hands-on experience in executing complete PD ownership from netlist to GDS2 including HM level...

Key Responsibilities: Lead the architecture, design, and integration of SoC-wide clocking networks including clock generation (PLLs, DLLs), distribution, gating, and domain crossing strategies. Define and optimize power-performance-area (PPA) trade-offs for complex clocking and circuit topologies. Collaborate cross-functionally with RTL, physical design, verification, and DFT teams to deliver end-to-end SoC clocking and custom IP. Own the technical roadmap and methodology improvements for clocking, timing closure, and custom circuits. Mentor and technically guide a team of junior and senior designers. Review and approve specifications, schematics, simulations, and post-layout signoff for hig...

Roles and Responsibilities: Perform RTL-to-GDSII implementation including floorplanning, placement, clock tree synthesis (CTS), routing, and timing closure. Work on P&R flows using tools such as Cadence Innovus / Synopsys ICC2 . Handle timing analysis and sign-off using PrimeTime / Tempus . Perform power planning, IR-drop, and EM analysis to meet reliability targets. Execute DFM closure DRC/LVS/ANT checks using Calibre . Implement ECOs for timing, functionality, and metal fixes. Work closely with front-end, verification, and DFT teams to ensure full-chip integration and timing convergence. Optimize Power, Performance, and Area (PPA) for block- and top-level designs. Contribute to flow automa...

Design and optimize analog and digital circuit layouts. Ensure layout designs meet all design specifications and industry standards. Collaborate with cross-functional teams including circuit designers and verification engineers. Required Candidate profile Knowledge of CMOS, BiCMOS, and bipolar technologies. Experience with EDA tools such as Cadence Virtuoso and Mentor Graphics. Ability to work collaboratively in a team environment. Perks and benefits Employee discounts, free meals, or snacks.

Responsible for high performance microprocessor blocks RTL to GDSII implementation Perform block level synthesis, floor-planning, placement and routing. Close the design to meet timing, power budget and area. Implement ECO's to address functional bugs and timing violations. Team player, with good problem solving and communication skills. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 5-8 years industry experience in physical design methodology. Good knowledge and hands on experience in physical design methodology which include logic synthesis,placement, clock tree synthesis, routing . Should be knowledgeable in physical ...

Responsible for high performance microprocessor blocks RTL to GDSII implementation Perform block level synthesis, floor-planning, placement and routing. Close the design to meet timing, power budget and area. Implement ECO's to address functional bugs and timing violations. Team player, with good problem solving and communication skills. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8-10 years of industry experience in physical design methodology. Good knowledge and hands-on experience in physical design methodology, which includes logic synthesis, placement, clock tree synthesis, routing. Should be knowledgeable in phy...

Job Details: Develops the logic design, register transfer level (RTL) coding, and simulation for graphics IPs (including graphics, compute, display, and media) required to generate cell libraries, functional units, and the GPU IP block for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly across verif...

Your Role Design, configure, and support SAP DRC solutions across global landscapes. Collaborate with cross-functional teams to gather requirements and deliver compliant reporting solutions. Ensure alignment with local tax and e-invoicing regulations. Troubleshoot and resolve issues related to DRC configurations and integrations. Support testing, documentation, and deployment activities. Your Profile You have612 years of experience in SAP, with strong exposure to SAP DRC. Hands-on experience in implementing or supporting SAP DRC/ACR solutions. Good understanding of e-invoicing, statutory reporting, and compliance requirements. Familiarity with SAP S/4HANA and integration with external tax sy...

Job Details: Job Description: As an IP Structural/Physical Design Engineer, you will be working alongside Elite IP and SoC design teams to deliver next-generation Xeon products and related IPs for Server markets. We are looking for candidates with experience as physical design engineers as part of the Structural Design Expert Team in the IP organization. You will be fluent in all aspects of IP physical design flow from high-level block design to synthesis, place and route and timing and power convergence to build a design database that is ready for manufacturing. Your responsibilities will include all aspects of RTL2GDSII physical design flow convergence including but not be limited to: Over...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performanc...

Performs physical design implementation of CPU designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to improve current and future CPU microarchitectures closely ...

EdTech Publishing 3 (views) Delhi Full Time Job role insights Date posted October 15, 2025 Hiring location Delhi Career level Experienced Qualification Bachelor Degree Experience 1 year Gender Any Gender Show more Hide less Description Aditya Ranjan Publications is hiring a Scriptwriter. Click here to explore more vacancies - https://obelabs.com/jobs/ Click here to join our Telegram channel - https://t.me/OBElabs #Jobs in Edtech Show more Hide less Skills Scriptwriter Interested in this job? 30 days left to apply Apply now Similar jobs View all jobs Adda Education is hiring immediately a Manager -Jobs in Edtech- #1 Apply fast! by Adda247 in EdTech Adda Education is hiring a Manager - Custome...

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Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Extensive experience in Place & Route with FC or Innovus is an absolute must Complete ASIC flow with low power, performance and area optimization techniques Experience with STA using Primetime and/or Tempus is required Proficient in constraint...

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Enginee...

At EY, youll have the chance to build a career as unique as you are, with the global scale, support, inclusive culture and technology to become the best version of you. And were counting on your unique voice and perspective to help EY become even better, too. Join us and build an exceptional experience for yourself, and a better working world for all. SAP DRC Expert Senior Consultant We are seeking a highly skilled SAP DRC Specialist with extensive experience in E-invoicing & E-Reporting. The ideal candidate will be responsible for leading implementation of SAP Digital Compliance and E-invoicing solutions to ensure compliance with global regulatory requirements. This role involves working cl...

At EY, youll have the chance to build a career as unique as you are, with the global scale, support, inclusive culture and technology to become the best version of you. And were counting on your unique voice and perspective to help EY become even better, too. Join us and build an exceptional experience for yourself, and a better working world for all. SAP DRC Expert Senior Consultant We are seeking a highly skilled SAP DRC Specialist with extensive experience in E-invoicing & E-Reporting. The ideal candidate will be responsible for leading implementation of SAP Digital Compliance and E-invoicing solutions to ensure compliance with global regulatory requirements. This role involves working cl...

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements Minimum Qualifications: Bachelor's degree in Computer Sci...

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer ...

General Summary: Physical Implementation activities for Sub systems which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Knowledge in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Knowledge in Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints...